2 * The PCI Utilities -- List All PCI Devices
4 * Copyright (c) 1997--2006 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL.
19 static int verbose; /* Show detailed information */
20 static int buscentric_view; /* Show bus addresses/IRQ's instead of CPU-visible ones */
21 static int show_hex; /* Show contents of config space as hexadecimal numbers */
22 static struct pci_filter filter; /* Device filter */
23 static int show_tree; /* Show bus tree */
24 static int machine_readable; /* Generate machine-readable output */
25 static int map_mode; /* Bus mapping mode enabled */
26 static int show_domains; /* Show domain numbers (0=disabled, 1=auto-detected, 2=requested) */
28 const char program_name[] = "lspci";
30 static char options[] = "nvbxs:d:ti:mgMD" GENERIC_OPTIONS ;
32 static char help_msg[] = "\
33 Usage: lspci [<switches>]\n\
36 -n\t\tShow numeric ID's\n\
37 -nn\t\tShow both textual and numeric ID's (names & numbers)\n\
38 -b\t\tBus-centric view (PCI addresses and IRQ's instead of those seen by the CPU)\n\
39 -x\t\tShow hex-dump of the standard portion of config space\n\
40 -xxx\t\tShow hex-dump of the whole config space (dangerous; root only)\n\
41 -xxxx\t\tShow hex-dump of the 4096-byte extended config space (root only)\n\
42 -s [[[[<domain>]:]<bus>]:][<slot>][.[<func>]]\tShow only devices in selected slots\n\
43 -d [<vendor>]:[<device>]\tShow only selected devices\n\
44 -t\t\tShow bus tree\n\
45 -m\t\tProduce machine-readable output\n\
46 -i <file>\tUse specified ID database instead of %s\n\
47 -D\t\tAlways show domain numbers\n\
48 -M\t\tEnable `bus mapping' mode (dangerous; root only)\n"
52 /* Communication with libpci */
54 static struct pci_access *pacc;
57 * If we aren't being compiled by GCC, use xmalloc() instead of alloca().
58 * This increases our memory footprint, but only slightly since we don't
64 #define alloca xmalloc
67 /* Our view of the PCI bus */
72 unsigned int config_cached, config_bufsize;
73 byte *config; /* Cached configuration space data */
74 byte *present; /* Maps which configuration bytes are present */
77 static struct device *first_dev;
78 static int seen_errors;
81 config_fetch(struct device *d, unsigned int pos, unsigned int len)
83 unsigned int end = pos+len;
86 while (pos < d->config_bufsize && len && d->present[pos])
88 while (pos+len <= d->config_bufsize && len && d->present[pos+len-1])
93 if (end > d->config_bufsize)
95 int orig_size = d->config_bufsize;
96 while (end > d->config_bufsize)
97 d->config_bufsize *= 2;
98 d->config = xrealloc(d->config, d->config_bufsize);
99 d->present = xrealloc(d->present, d->config_bufsize);
100 bzero(d->present + orig_size, d->config_bufsize - orig_size);
102 result = pci_read_block(d->dev, pos, d->config + pos, len);
104 memset(d->present + pos, 1, len);
108 static struct device *
109 scan_device(struct pci_dev *p)
113 if (p->domain && !show_domains)
115 if (!pci_filter_match(&filter, p))
117 d = xmalloc(sizeof(struct device));
118 bzero(d, sizeof(*d));
120 d->config_cached = d->config_bufsize = 64;
121 d->config = xmalloc(64);
122 d->present = xmalloc(64);
123 memset(d->present, 1, 64);
124 if (!pci_read_block(p, 0, d->config, 64))
126 fprintf(stderr, "lspci: Unable to read the standard configuration space header of device %04x:%02x:%02x.%d\n",
127 p->domain, p->bus, p->dev, p->func);
131 if ((d->config[PCI_HEADER_TYPE] & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
133 /* For cardbus bridges, we need to fetch 64 bytes more to get the
134 * full standard header... */
135 if (config_fetch(d, 64, 64))
136 d->config_cached += 64;
138 pci_setup_cache(p, d->config, d->config_cached);
139 pci_fill_info(p, PCI_FILL_IDENT | PCI_FILL_CLASS | PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE | PCI_FILL_SIZES);
150 for(p=pacc->devices; p; p=p->next)
151 if (d = scan_device(p))
158 /* Config space accesses */
161 check_conf_range(struct device *d, unsigned int pos, unsigned int len)
164 if (!d->present[pos])
165 die("Internal bug: Accessing non-read configuration byte at position %x", pos);
171 get_conf_byte(struct device *d, unsigned int pos)
173 check_conf_range(d, pos, 1);
174 return d->config[pos];
178 get_conf_word(struct device *d, unsigned int pos)
180 check_conf_range(d, pos, 2);
181 return d->config[pos] | (d->config[pos+1] << 8);
185 get_conf_long(struct device *d, unsigned int pos)
187 check_conf_range(d, pos, 4);
188 return d->config[pos] |
189 (d->config[pos+1] << 8) |
190 (d->config[pos+2] << 16) |
191 (d->config[pos+3] << 24);
197 compare_them(const void *A, const void *B)
199 const struct pci_dev *a = (*(const struct device **)A)->dev;
200 const struct pci_dev *b = (*(const struct device **)B)->dev;
202 if (a->domain < b->domain)
204 if (a->domain > b->domain)
214 if (a->func < b->func)
216 if (a->func > b->func)
224 struct device **index, **h, **last_dev;
229 for(d=first_dev; d; d=d->next)
231 h = index = alloca(sizeof(struct device *) * cnt);
232 for(d=first_dev; d; d=d->next)
234 qsort(index, cnt, sizeof(struct device *), compare_them);
235 last_dev = &first_dev;
240 last_dev = &(*h)->next;
248 #define FLAG(x,y) ((x & y) ? '+' : '-')
251 show_slot_name(struct device *d)
253 struct pci_dev *p = d->dev;
255 if (!machine_readable ? show_domains : (p->domain || show_domains >= 2))
256 printf("%04x:", p->domain);
257 printf("%02x:%02x.%d", p->bus, p->dev, p->func);
261 show_terse(struct device *d)
264 struct pci_dev *p = d->dev;
265 char classbuf[128], devbuf[128];
269 pci_lookup_name(pacc, classbuf, sizeof(classbuf),
272 pci_lookup_name(pacc, devbuf, sizeof(devbuf),
273 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
274 p->vendor_id, p->device_id));
275 if (c = get_conf_byte(d, PCI_REVISION_ID))
276 printf(" (rev %02x)", c);
280 c = get_conf_byte(d, PCI_CLASS_PROG);
281 x = pci_lookup_name(pacc, devbuf, sizeof(devbuf),
282 PCI_LOOKUP_PROGIF | PCI_LOOKUP_NO_NUMBERS,
286 printf(" (prog-if %02x", c);
296 show_size(pciaddr_t x)
302 printf("%d", (int) x);
303 else if (x < 1048576)
304 printf("%dK", (int)(x / 1024));
305 else if (x < 0x80000000)
306 printf("%dM", (int)(x / 1048576));
308 printf(PCIADDR_T_FMT, x);
313 show_bases(struct device *d, int cnt)
315 struct pci_dev *p = d->dev;
316 word cmd = get_conf_word(d, PCI_COMMAND);
321 pciaddr_t pos = p->base_addr[i];
322 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->size[i] : 0;
323 u32 flg = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
324 if (flg == 0xffffffff)
326 if (!pos && !flg && !len)
329 printf("\tRegion %d: ", i);
332 if (pos && !flg) /* Reported by the OS, but not by the device */
334 printf("[virtual] ");
337 if (flg & PCI_BASE_ADDRESS_SPACE_IO)
339 pciaddr_t a = pos & PCI_BASE_ADDRESS_IO_MASK;
340 printf("I/O ports at ");
342 printf(PCIADDR_PORT_FMT, a);
343 else if (flg & PCI_BASE_ADDRESS_IO_MASK)
346 printf("<unassigned>");
347 if (!(cmd & PCI_COMMAND_IO))
348 printf(" [disabled]");
352 int t = flg & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
353 pciaddr_t a = pos & PCI_ADDR_MEM_MASK;
357 printf("Memory at ");
358 if (t == PCI_BASE_ADDRESS_MEM_TYPE_64)
362 printf("<invalid-64bit-slot>");
368 z = get_conf_long(d, PCI_BASE_ADDRESS_0 + 4*i);
371 u32 y = a & 0xffffffff;
373 printf("%08x%08x", z, y);
375 printf("<unassigned>");
383 printf(PCIADDR_T_FMT, a);
385 printf(((flg & PCI_BASE_ADDRESS_MEM_MASK) || z) ? "<ignored>" : "<unassigned>");
387 printf(" (%s, %sprefetchable)",
388 (t == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32-bit" :
389 (t == PCI_BASE_ADDRESS_MEM_TYPE_64) ? "64-bit" :
390 (t == PCI_BASE_ADDRESS_MEM_TYPE_1M) ? "low-1M" : "type 3",
391 (flg & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
392 if (!(cmd & PCI_COMMAND_MEMORY))
393 printf(" [disabled]");
401 show_pm(struct device *d, int where, int cap)
404 static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
406 printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
409 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
410 FLAG(cap, PCI_PM_CAP_PME_CLOCK),
411 FLAG(cap, PCI_PM_CAP_DSI),
412 FLAG(cap, PCI_PM_CAP_D1),
413 FLAG(cap, PCI_PM_CAP_D2),
414 pm_aux_current[(cap >> 6) & 7],
415 FLAG(cap, PCI_PM_CAP_PME_D0),
416 FLAG(cap, PCI_PM_CAP_PME_D1),
417 FLAG(cap, PCI_PM_CAP_PME_D2),
418 FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
419 FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
420 if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
422 t = get_conf_word(d, where + PCI_PM_CTRL);
423 printf("\t\tStatus: D%d PME-Enable%c DSel=%d DScale=%d PME%c\n",
424 t & PCI_PM_CTRL_STATE_MASK,
425 FLAG(t, PCI_PM_CTRL_PME_ENABLE),
426 (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
427 (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
428 FLAG(t, PCI_PM_CTRL_PME_STATUS));
429 b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
431 printf("\t\tBridge: PM%c B3%c\n",
432 FLAG(t, PCI_PM_BPCC_ENABLE),
433 FLAG(~t, PCI_PM_PPB_B2_B3));
437 format_agp_rate(int rate, char *buf, int agp3)
447 c += sprintf(c, "x%d", 1 << (i + 2*agp3));
452 strcpy(buf, "<none>");
456 show_agp(struct device *d, int where, int cap)
463 ver = (cap >> 4) & 0x0f;
465 printf("AGP version %x.%x\n", ver, rev);
468 if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
470 t = get_conf_long(d, where + PCI_AGP_STATUS);
471 if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
473 format_agp_rate(t & 7, rate, agp3);
474 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
475 ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
476 FLAG(t, PCI_AGP_STATUS_ISOCH),
477 ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
478 ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
479 FLAG(t, PCI_AGP_STATUS_SBA),
480 FLAG(t, PCI_AGP_STATUS_ITA_COH),
481 FLAG(t, PCI_AGP_STATUS_GART64),
482 FLAG(t, PCI_AGP_STATUS_HTRANS),
483 FLAG(t, PCI_AGP_STATUS_64BIT),
484 FLAG(t, PCI_AGP_STATUS_FW),
485 FLAG(t, PCI_AGP_STATUS_AGP3),
487 t = get_conf_long(d, where + PCI_AGP_COMMAND);
488 format_agp_rate(t & 7, rate, agp3);
489 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
490 ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
491 ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
492 ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
493 FLAG(t, PCI_AGP_COMMAND_SBA),
494 FLAG(t, PCI_AGP_COMMAND_AGP),
495 FLAG(t, PCI_AGP_COMMAND_GART64),
496 FLAG(t, PCI_AGP_COMMAND_64BIT),
497 FLAG(t, PCI_AGP_COMMAND_FW),
502 show_pcix_nobridge(struct device *d, int where)
506 static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
508 printf("PCI-X non-bridge device\n");
513 if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
516 command = get_conf_word(d, where + PCI_PCIX_COMMAND);
517 status = get_conf_long(d, where + PCI_PCIX_STATUS);
518 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
519 FLAG(command, PCI_PCIX_COMMAND_DPERE),
520 FLAG(command, PCI_PCIX_COMMAND_ERO),
521 1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
522 max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
523 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
524 ((status >> 8) & 0xff),
525 ((status >> 3) & 0x1f),
526 (status & PCI_PCIX_STATUS_FUNCTION),
527 FLAG(status, PCI_PCIX_STATUS_64BIT),
528 FLAG(status, PCI_PCIX_STATUS_133MHZ),
529 FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
530 FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
531 ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
532 1 << (9 + ((status >> 21) & 3U)),
533 max_outstanding[(status >> 23) & 7U],
534 1 << (3 + ((status >> 26) & 7U)),
535 FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
536 FLAG(status, PCI_PCIX_STATUS_266MHZ),
537 FLAG(status, PCI_PCIX_STATUS_533MHZ));
541 show_pcix_bridge(struct device *d, int where)
543 static const char * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
545 u32 status, upstcr, downstcr;
547 printf("PCI-X bridge device\n");
552 if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
555 secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
556 printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
557 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
558 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
559 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
560 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
561 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
562 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
563 sec_clock_freq[(secstatus >> 6) & 7]);
564 status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
565 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
566 ((status >> 8) & 0xff),
567 ((status >> 3) & 0x1f),
568 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
569 FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
570 FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
571 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
572 FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
573 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
574 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
575 upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
576 printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
577 (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
578 (upstcr >> 16) & 0xffff);
579 downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
580 printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
581 (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
582 (downstcr >> 16) & 0xffff);
586 show_pcix(struct device *d, int where)
588 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
590 case PCI_HEADER_TYPE_NORMAL:
591 show_pcix_nobridge(d, where);
593 case PCI_HEADER_TYPE_BRIDGE:
594 show_pcix_bridge(d, where);
600 ht_link_width(unsigned width)
602 static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
603 return widths[width];
607 ht_link_freq(unsigned freq)
609 static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
610 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
615 show_ht_pri(struct device *d, int where, int cmd)
617 u16 lctr0, lcnf0, lctr1, lcnf1, eh;
618 u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
621 printf("HyperTransport: Slave or Primary Interface\n");
625 if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
627 rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
628 if (rid < 0x23 && rid > 0x11)
629 printf("\t\t!!! Possibly incomplete decoding\n");
632 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n";
634 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n";
636 (cmd & PCI_HT_PRI_CMD_BUID),
637 (cmd & PCI_HT_PRI_CMD_UC) >> 5,
638 FLAG(cmd, PCI_HT_PRI_CMD_MH),
639 FLAG(cmd, PCI_HT_PRI_CMD_DD),
640 FLAG(cmd, PCI_HT_PRI_CMD_DUL));
641 lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
643 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
645 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
647 FLAG(lctr0, PCI_HT_LCTR_CFLE),
648 FLAG(lctr0, PCI_HT_LCTR_CST),
649 FLAG(lctr0, PCI_HT_LCTR_CFE),
650 FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
651 FLAG(lctr0, PCI_HT_LCTR_INIT),
652 FLAG(lctr0, PCI_HT_LCTR_EOC),
653 FLAG(lctr0, PCI_HT_LCTR_TXO),
654 (lctr0 & PCI_HT_LCTR_CRCERR) >> 8,
655 FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
656 FLAG(lctr0, PCI_HT_LCTR_LSEN),
657 FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
658 FLAG(lctr0, PCI_HT_LCTR_64B));
659 lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
661 fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
663 fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
665 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
666 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
667 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
668 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
669 FLAG(lcnf0, PCI_HT_LCNF_DFI),
670 FLAG(lcnf0, PCI_HT_LCNF_DFO),
671 FLAG(lcnf0, PCI_HT_LCNF_DFIE),
672 FLAG(lcnf0, PCI_HT_LCNF_DFOE));
673 lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
675 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
677 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
679 FLAG(lctr1, PCI_HT_LCTR_CFLE),
680 FLAG(lctr1, PCI_HT_LCTR_CST),
681 FLAG(lctr1, PCI_HT_LCTR_CFE),
682 FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
683 FLAG(lctr1, PCI_HT_LCTR_INIT),
684 FLAG(lctr1, PCI_HT_LCTR_EOC),
685 FLAG(lctr1, PCI_HT_LCTR_TXO),
686 (lctr1 & PCI_HT_LCTR_CRCERR) >> 8,
687 FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
688 FLAG(lctr1, PCI_HT_LCTR_LSEN),
689 FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
690 FLAG(lctr1, PCI_HT_LCTR_64B));
691 lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
693 fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
695 fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
697 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
698 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
699 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
700 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
701 FLAG(lcnf1, PCI_HT_LCNF_DFI),
702 FLAG(lcnf1, PCI_HT_LCNF_DFO),
703 FLAG(lcnf1, PCI_HT_LCNF_DFIE),
704 FLAG(lcnf1, PCI_HT_LCNF_DFOE));
705 printf("\t\tRevision ID: %u.%02u\n",
706 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
709 lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
710 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
711 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
712 FLAG(lfrer0, PCI_HT_LFRER_PROT),
713 FLAG(lfrer0, PCI_HT_LFRER_OV),
714 FLAG(lfrer0, PCI_HT_LFRER_EOC),
715 FLAG(lfrer0, PCI_HT_LFRER_CTLT));
716 lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
717 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
718 FLAG(lfcap0, PCI_HT_LFCAP_200),
719 FLAG(lfcap0, PCI_HT_LFCAP_300),
720 FLAG(lfcap0, PCI_HT_LFCAP_400),
721 FLAG(lfcap0, PCI_HT_LFCAP_500),
722 FLAG(lfcap0, PCI_HT_LFCAP_600),
723 FLAG(lfcap0, PCI_HT_LFCAP_800),
724 FLAG(lfcap0, PCI_HT_LFCAP_1000),
725 FLAG(lfcap0, PCI_HT_LFCAP_1200),
726 FLAG(lfcap0, PCI_HT_LFCAP_1400),
727 FLAG(lfcap0, PCI_HT_LFCAP_1600),
728 FLAG(lfcap0, PCI_HT_LFCAP_VEND));
729 ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
730 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
731 FLAG(ftr, PCI_HT_FTR_ISOCFC),
732 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
733 FLAG(ftr, PCI_HT_FTR_CRCTM),
734 FLAG(ftr, PCI_HT_FTR_ECTLT),
735 FLAG(ftr, PCI_HT_FTR_64BA),
736 FLAG(ftr, PCI_HT_FTR_UIDRD));
737 lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
738 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
739 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
740 FLAG(lfrer1, PCI_HT_LFRER_PROT),
741 FLAG(lfrer1, PCI_HT_LFRER_OV),
742 FLAG(lfrer1, PCI_HT_LFRER_EOC),
743 FLAG(lfrer1, PCI_HT_LFRER_CTLT));
744 lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
745 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
746 FLAG(lfcap1, PCI_HT_LFCAP_200),
747 FLAG(lfcap1, PCI_HT_LFCAP_300),
748 FLAG(lfcap1, PCI_HT_LFCAP_400),
749 FLAG(lfcap1, PCI_HT_LFCAP_500),
750 FLAG(lfcap1, PCI_HT_LFCAP_600),
751 FLAG(lfcap1, PCI_HT_LFCAP_800),
752 FLAG(lfcap1, PCI_HT_LFCAP_1000),
753 FLAG(lfcap1, PCI_HT_LFCAP_1200),
754 FLAG(lfcap1, PCI_HT_LFCAP_1400),
755 FLAG(lfcap1, PCI_HT_LFCAP_1600),
756 FLAG(lfcap1, PCI_HT_LFCAP_VEND));
757 eh = get_conf_word(d, where + PCI_HT_PRI_EH);
758 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
759 FLAG(eh, PCI_HT_EH_PFLE),
760 FLAG(eh, PCI_HT_EH_OFLE),
761 FLAG(eh, PCI_HT_EH_PFE),
762 FLAG(eh, PCI_HT_EH_OFE),
763 FLAG(eh, PCI_HT_EH_EOCFE),
764 FLAG(eh, PCI_HT_EH_RFE),
765 FLAG(eh, PCI_HT_EH_CRCFE),
766 FLAG(eh, PCI_HT_EH_SERRFE),
767 FLAG(eh, PCI_HT_EH_CF),
768 FLAG(eh, PCI_HT_EH_RE),
769 FLAG(eh, PCI_HT_EH_PNFE),
770 FLAG(eh, PCI_HT_EH_ONFE),
771 FLAG(eh, PCI_HT_EH_EOCNFE),
772 FLAG(eh, PCI_HT_EH_RNFE),
773 FLAG(eh, PCI_HT_EH_CRCNFE),
774 FLAG(eh, PCI_HT_EH_SERRNFE));
775 mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
776 mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
777 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
778 bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
779 printf("\t\tBus Number: %02x\n", bn);
783 show_ht_sec(struct device *d, int where, int cmd)
785 u16 lctr, lcnf, ftr, eh;
786 u8 rid, lfrer, lfcap, mbu, mlu;
789 printf("HyperTransport: Host or Secondary Interface\n");
793 if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
795 rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
796 if (rid < 0x23 && rid > 0x11)
797 printf("\t\t!!! Possibly incomplete decoding\n");
800 fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
802 fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
804 FLAG(cmd, PCI_HT_SEC_CMD_WR),
805 FLAG(cmd, PCI_HT_SEC_CMD_DE),
806 (cmd & PCI_HT_SEC_CMD_DN) >> 2,
807 FLAG(cmd, PCI_HT_SEC_CMD_CS),
808 FLAG(cmd, PCI_HT_SEC_CMD_HH),
809 FLAG(cmd, PCI_HT_SEC_CMD_AS),
810 FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
811 FLAG(cmd, PCI_HT_SEC_CMD_DUL));
812 lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
814 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
816 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
818 FLAG(lctr, PCI_HT_LCTR_CFLE),
819 FLAG(lctr, PCI_HT_LCTR_CST),
820 FLAG(lctr, PCI_HT_LCTR_CFE),
821 FLAG(lctr, PCI_HT_LCTR_LKFAIL),
822 FLAG(lctr, PCI_HT_LCTR_INIT),
823 FLAG(lctr, PCI_HT_LCTR_EOC),
824 FLAG(lctr, PCI_HT_LCTR_TXO),
825 (lctr & PCI_HT_LCTR_CRCERR) >> 8,
826 FLAG(lctr, PCI_HT_LCTR_ISOCEN),
827 FLAG(lctr, PCI_HT_LCTR_LSEN),
828 FLAG(lctr, PCI_HT_LCTR_EXTCTL),
829 FLAG(lctr, PCI_HT_LCTR_64B));
830 lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
832 fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
834 fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
836 ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
837 ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
838 ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
839 ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
840 FLAG(lcnf, PCI_HT_LCNF_DFI),
841 FLAG(lcnf, PCI_HT_LCNF_DFO),
842 FLAG(lcnf, PCI_HT_LCNF_DFIE),
843 FLAG(lcnf, PCI_HT_LCNF_DFOE));
844 printf("\t\tRevision ID: %u.%02u\n",
845 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
848 lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
849 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
850 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
851 FLAG(lfrer, PCI_HT_LFRER_PROT),
852 FLAG(lfrer, PCI_HT_LFRER_OV),
853 FLAG(lfrer, PCI_HT_LFRER_EOC),
854 FLAG(lfrer, PCI_HT_LFRER_CTLT));
855 lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
856 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
857 FLAG(lfcap, PCI_HT_LFCAP_200),
858 FLAG(lfcap, PCI_HT_LFCAP_300),
859 FLAG(lfcap, PCI_HT_LFCAP_400),
860 FLAG(lfcap, PCI_HT_LFCAP_500),
861 FLAG(lfcap, PCI_HT_LFCAP_600),
862 FLAG(lfcap, PCI_HT_LFCAP_800),
863 FLAG(lfcap, PCI_HT_LFCAP_1000),
864 FLAG(lfcap, PCI_HT_LFCAP_1200),
865 FLAG(lfcap, PCI_HT_LFCAP_1400),
866 FLAG(lfcap, PCI_HT_LFCAP_1600),
867 FLAG(lfcap, PCI_HT_LFCAP_VEND));
868 ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
869 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
870 FLAG(ftr, PCI_HT_FTR_ISOCFC),
871 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
872 FLAG(ftr, PCI_HT_FTR_CRCTM),
873 FLAG(ftr, PCI_HT_FTR_ECTLT),
874 FLAG(ftr, PCI_HT_FTR_64BA),
875 FLAG(ftr, PCI_HT_FTR_UIDRD),
876 FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
877 FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
878 if (ftr & PCI_HT_SEC_FTR_EXTRS)
880 eh = get_conf_word(d, where + PCI_HT_SEC_EH);
881 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
882 FLAG(eh, PCI_HT_EH_PFLE),
883 FLAG(eh, PCI_HT_EH_OFLE),
884 FLAG(eh, PCI_HT_EH_PFE),
885 FLAG(eh, PCI_HT_EH_OFE),
886 FLAG(eh, PCI_HT_EH_EOCFE),
887 FLAG(eh, PCI_HT_EH_RFE),
888 FLAG(eh, PCI_HT_EH_CRCFE),
889 FLAG(eh, PCI_HT_EH_SERRFE),
890 FLAG(eh, PCI_HT_EH_CF),
891 FLAG(eh, PCI_HT_EH_RE),
892 FLAG(eh, PCI_HT_EH_PNFE),
893 FLAG(eh, PCI_HT_EH_ONFE),
894 FLAG(eh, PCI_HT_EH_EOCNFE),
895 FLAG(eh, PCI_HT_EH_RNFE),
896 FLAG(eh, PCI_HT_EH_CRCNFE),
897 FLAG(eh, PCI_HT_EH_SERRNFE));
898 mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
899 mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
900 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
905 show_ht(struct device *d, int where, int cmd)
909 switch (cmd & PCI_HT_CMD_TYP_HI)
911 case PCI_HT_CMD_TYP_HI_PRI:
912 show_ht_pri(d, where, cmd);
914 case PCI_HT_CMD_TYP_HI_SEC:
915 show_ht_sec(d, where, cmd);
919 type = cmd & PCI_HT_CMD_TYP;
922 case PCI_HT_CMD_TYP_SW:
923 printf("HyperTransport: Switch\n");
925 case PCI_HT_CMD_TYP_IDC:
926 printf("HyperTransport: Interrupt Discovery and Configuration\n");
928 case PCI_HT_CMD_TYP_RID:
929 printf("HyperTransport: Revision ID: %u.%02u\n",
930 (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
932 case PCI_HT_CMD_TYP_UIDC:
933 printf("HyperTransport: UnitID Clumping\n");
935 case PCI_HT_CMD_TYP_ECSA:
936 printf("HyperTransport: Extended Configuration Space Access\n");
938 case PCI_HT_CMD_TYP_AM:
939 printf("HyperTransport: Address Mapping\n");
941 case PCI_HT_CMD_TYP_MSIM:
942 printf("HyperTransport: MSI Mapping\n");
944 case PCI_HT_CMD_TYP_DR:
945 printf("HyperTransport: DirectRoute\n");
947 case PCI_HT_CMD_TYP_VCS:
948 printf("HyperTransport: VCSet\n");
950 case PCI_HT_CMD_TYP_RM:
951 printf("HyperTransport: Retry Mode\n");
953 case PCI_HT_CMD_TYP_X86:
954 printf("HyperTransport: X86 (reserved)\n");
957 printf("HyperTransport: #%02x\n", type >> 11);
962 show_rom(struct device *d, int reg)
964 struct pci_dev *p = d->dev;
965 pciaddr_t rom = p->rom_base_addr;
966 pciaddr_t len = (p->known_fields & PCI_FILL_SIZES) ? p->rom_size : 0;
967 u32 flg = get_conf_long(d, reg);
968 word cmd = get_conf_word(d, PCI_COMMAND);
970 if (!rom && !flg && !len)
973 if ((rom & PCI_ROM_ADDRESS_MASK) && !(flg & PCI_ROM_ADDRESS_MASK))
975 printf("[virtual] ");
978 printf("Expansion ROM at ");
979 if (rom & PCI_ROM_ADDRESS_MASK)
980 printf(PCIADDR_T_FMT, rom & PCI_ROM_ADDRESS_MASK);
981 else if (flg & PCI_ROM_ADDRESS_MASK)
984 printf("<unassigned>");
985 if (!(flg & PCI_ROM_ADDRESS_ENABLE))
986 printf(" [disabled]");
987 else if (!(cmd & PCI_COMMAND_MEMORY))
988 printf(" [disabled by cmd]");
994 show_msi(struct device *d, int where, int cap)
1000 printf("Message Signalled Interrupts: Mask%c 64bit%c Queue=%d/%d Enable%c\n",
1001 FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
1002 FLAG(cap, PCI_MSI_FLAGS_64BIT),
1003 (cap & PCI_MSI_FLAGS_QSIZE) >> 4,
1004 (cap & PCI_MSI_FLAGS_QMASK) >> 1,
1005 FLAG(cap, PCI_MSI_FLAGS_ENABLE));
1008 is64 = cap & PCI_MSI_FLAGS_64BIT;
1009 if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
1011 printf("\t\tAddress: ");
1014 t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
1015 w = get_conf_word(d, where + PCI_MSI_DATA_64);
1019 w = get_conf_word(d, where + PCI_MSI_DATA_32);
1020 t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
1021 printf("%08x Data: %04x\n", t, w);
1022 if (cap & PCI_MSI_FLAGS_MASK_BIT)
1028 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_64, 8))
1030 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_64);
1031 pending = get_conf_long(d, where + PCI_MSI_PENDING_64);
1035 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_32, 8))
1037 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_32);
1038 pending = get_conf_long(d, where + PCI_MSI_PENDING_32);
1040 printf("\t\tMasking: %08x Pending: %08x\n", mask, pending);
1044 static void show_vendor(void)
1046 printf("Vendor Specific Information\n");
1049 static void show_debug(void)
1051 printf("Debug port\n");
1054 static float power_limit(int value, int scale)
1056 static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
1057 return value * scales[scale];
1060 static const char *latency_l0s(int value)
1062 static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
1063 return latencies[value];
1066 static const char *latency_l1(int value)
1068 static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
1069 return latencies[value];
1072 static void show_express_dev(struct device *d, int where, int type)
1077 t = get_conf_long(d, where + PCI_EXP_DEVCAP);
1078 printf("\t\tDevice: Supported: MaxPayload %d bytes, PhantFunc %d, ExtTag%c\n",
1079 128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
1080 (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1,
1081 FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
1082 printf("\t\tDevice: Latency L0s %s, L1 %s\n",
1083 latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
1084 latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
1085 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
1086 (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
1087 printf("\t\tDevice: AtnBtn%c AtnInd%c PwrInd%c\n",
1088 FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
1089 FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
1090 if (type == PCI_EXP_TYPE_UPSTREAM)
1091 printf("\t\tDevice: SlotPowerLimit %f\n",
1092 power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
1093 (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
1095 w = get_conf_word(d, where + PCI_EXP_DEVCTL);
1096 printf("\t\tDevice: Errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
1097 FLAG(w, PCI_EXP_DEVCTL_CERE),
1098 FLAG(w, PCI_EXP_DEVCTL_NFERE),
1099 FLAG(w, PCI_EXP_DEVCTL_FERE),
1100 FLAG(w, PCI_EXP_DEVCTL_URRE));
1101 printf("\t\tDevice: RlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c\n",
1102 FLAG(w, PCI_EXP_DEVCTL_RELAXED),
1103 FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
1104 FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
1105 FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
1106 FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
1107 printf("\t\tDevice: MaxPayload %d bytes, MaxReadReq %d bytes\n",
1108 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
1109 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
1112 static char *link_speed(int speed)
1123 static char *aspm_support(int code)
1136 static const char *aspm_enabled(int code)
1138 static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
1142 static void show_express_link(struct device *d, int where, int type)
1147 t = get_conf_long(d, where + PCI_EXP_LNKCAP);
1148 printf("\t\tLink: Supported Speed %s, Width x%d, ASPM %s, Port %d\n",
1149 link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
1150 aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
1152 printf("\t\tLink: Latency L0s %s, L1 %s\n",
1153 latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
1154 latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
1155 w = get_conf_word(d, where + PCI_EXP_LNKCTL);
1156 printf("\t\tLink: ASPM %s", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
1157 if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
1158 (type == PCI_EXP_TYPE_LEG_END))
1159 printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
1160 if (w & PCI_EXP_LNKCTL_DISABLE)
1161 printf(" Disabled");
1162 printf(" CommClk%c ExtSynch%c\n", FLAG(w, PCI_EXP_LNKCTL_CLOCK),
1163 FLAG(w, PCI_EXP_LNKCTL_XSYNCH));
1164 w = get_conf_word(d, where + PCI_EXP_LNKSTA);
1165 printf("\t\tLink: Speed %s, Width x%d\n",
1166 link_speed(w & PCI_EXP_LNKSTA_SPEED), (w & PCI_EXP_LNKSTA_WIDTH) >> 4);
1169 static const char *indicator(int code)
1171 static const char *names[] = { "Unknown", "On", "Blink", "Off" };
1175 static void show_express_slot(struct device *d, int where)
1180 t = get_conf_long(d, where + PCI_EXP_SLTCAP);
1181 printf("\t\tSlot: AtnBtn%c PwrCtrl%c MRL%c AtnInd%c PwrInd%c HotPlug%c Surpise%c\n",
1182 FLAG(t, PCI_EXP_SLTCAP_ATNB),
1183 FLAG(t, PCI_EXP_SLTCAP_PWRC),
1184 FLAG(t, PCI_EXP_SLTCAP_MRL),
1185 FLAG(t, PCI_EXP_SLTCAP_ATNI),
1186 FLAG(t, PCI_EXP_SLTCAP_PWRI),
1187 FLAG(t, PCI_EXP_SLTCAP_HPC),
1188 FLAG(t, PCI_EXP_SLTCAP_HPS));
1189 printf("\t\tSlot: Number %d, PowerLimit %f\n", t >> 19,
1190 power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7,
1191 (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15));
1192 w = get_conf_word(d, where + PCI_EXP_SLTCTL);
1193 printf("\t\tSlot: Enabled AtnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c\n",
1194 FLAG(w, PCI_EXP_SLTCTL_ATNB),
1195 FLAG(w, PCI_EXP_SLTCTL_PWRF),
1196 FLAG(w, PCI_EXP_SLTCTL_MRLS),
1197 FLAG(w, PCI_EXP_SLTCTL_PRSD),
1198 FLAG(w, PCI_EXP_SLTCTL_CMDC),
1199 FLAG(w, PCI_EXP_SLTCTL_HPIE));
1200 printf("\t\tSlot: AttnInd %s, PwrInd %s, Power%c\n",
1201 indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
1202 indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
1203 FLAG(w, w & PCI_EXP_SLTCTL_PWRC));
1206 static void show_express_root(struct device *d, int where)
1208 u16 w = get_conf_word(d, where + PCI_EXP_RTCTL);
1209 printf("\t\tRoot: Correctable%c Non-Fatal%c Fatal%c PME%c\n",
1210 FLAG(w, PCI_EXP_RTCTL_SECEE),
1211 FLAG(w, PCI_EXP_RTCTL_SENFEE),
1212 FLAG(w, PCI_EXP_RTCTL_SEFEE),
1213 FLAG(w, PCI_EXP_RTCTL_PMEIE));
1217 show_express(struct device *d, int where, int cap)
1219 int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1226 case PCI_EXP_TYPE_ENDPOINT:
1229 case PCI_EXP_TYPE_LEG_END:
1230 printf("Legacy Endpoint");
1232 case PCI_EXP_TYPE_ROOT_PORT:
1233 slot = cap & PCI_EXP_FLAGS_SLOT;
1234 printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1236 case PCI_EXP_TYPE_UPSTREAM:
1237 printf("Upstream Port");
1239 case PCI_EXP_TYPE_DOWNSTREAM:
1240 slot = cap & PCI_EXP_FLAGS_SLOT;
1241 printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1243 case PCI_EXP_TYPE_PCI_BRIDGE:
1244 printf("PCI/PCI-X Bridge");
1247 printf("Unknown type");
1249 printf(" IRQ %d\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1256 if (type == PCI_EXP_TYPE_ROOT_PORT)
1258 if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1261 show_express_dev(d, where, type);
1262 show_express_link(d, where, type);
1264 show_express_slot(d, where);
1265 if (type == PCI_EXP_TYPE_ROOT_PORT)
1266 show_express_root(d, where);
1270 show_msix(struct device *d, int where, int cap)
1274 printf("MSI-X: Enable%c Mask%c TabSize=%d\n",
1275 FLAG(cap, PCI_MSIX_ENABLE),
1276 FLAG(cap, PCI_MSIX_MASK),
1277 (cap & PCI_MSIX_TABSIZE) + 1);
1278 if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1281 off = get_conf_long(d, where + PCI_MSIX_TABLE);
1282 printf("\t\tVector table: BAR=%d offset=%08x\n",
1283 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1284 off = get_conf_long(d, where + PCI_MSIX_PBA);
1285 printf("\t\tPBA: BAR=%d offset=%08x\n",
1286 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1290 show_slotid(int cap)
1292 int esr = cap & 0xff;
1295 printf("Slot ID: %d slots, First%c, chassis %02x\n",
1296 esr & PCI_SID_ESR_NSLOTS,
1297 FLAG(esr, PCI_SID_ESR_FIC),
1302 show_ssvid(struct device *d, int where)
1304 u16 subsys_v, subsys_d;
1305 char ssnamebuf[256];
1307 if (!config_fetch(d, where, 8))
1309 subsys_v = get_conf_word(d, where + PCI_SSVID_VENDOR);
1310 subsys_d = get_conf_word(d, where + PCI_SSVID_DEVICE);
1311 printf("Subsystem: %s\n",
1312 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1313 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1314 d->dev->vendor_id, d->dev->device_id, subsys_v, subsys_d));
1318 show_aer(struct device *d UNUSED, int where UNUSED)
1320 printf("Advanced Error Reporting\n");
1324 show_vc(struct device *d UNUSED, int where UNUSED)
1326 printf("Virtual Channel\n");
1330 show_dsn(struct device *d, int where)
1333 if (!config_fetch(d, where + 4, 8))
1335 t1 = get_conf_long(d, where + 4);
1336 t2 = get_conf_long(d, where + 8);
1337 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
1338 t1 & 0xff, (t1 >> 8) & 0xff, (t1 >> 16) & 0xff, t1 >> 24,
1339 t2 & 0xff, (t2 >> 8) & 0xff, (t2 >> 16) & 0xff, t2 >> 24);
1343 show_pb(struct device *d UNUSED, int where UNUSED)
1345 printf("Power Budgeting\n");
1349 show_ext_caps(struct device *d)
1357 if (!config_fetch(d, where, 4))
1359 header = get_conf_long(d, where);
1362 id = header & 0xffff;
1363 printf("\tCapabilities: [%03x] ", where);
1366 case PCI_EXT_CAP_ID_AER:
1369 case PCI_EXT_CAP_ID_VC:
1372 case PCI_EXT_CAP_ID_DSN:
1375 case PCI_EXT_CAP_ID_PB:
1379 printf("Unknown (%d)\n", id);
1382 where = header >> 20;
1387 show_caps(struct device *d)
1389 int can_have_ext_caps = 0;
1391 if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1393 int where = get_conf_byte(d, PCI_CAPABILITY_LIST) & ~3;
1397 printf("\tCapabilities: ");
1398 if (!config_fetch(d, where, 4))
1400 puts("<access denied>");
1403 id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1404 next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1405 cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1406 printf("[%02x] ", where);
1409 printf("<chain broken>\n");
1415 show_pm(d, where, cap);
1417 case PCI_CAP_ID_AGP:
1418 show_agp(d, where, cap);
1420 case PCI_CAP_ID_VPD:
1421 printf("Vital Product Data\n");
1423 case PCI_CAP_ID_SLOTID:
1426 case PCI_CAP_ID_MSI:
1427 show_msi(d, where, cap);
1429 case PCI_CAP_ID_PCIX:
1430 show_pcix(d, where);
1431 can_have_ext_caps = 1;
1434 show_ht(d, where, cap);
1436 case PCI_CAP_ID_VNDR:
1439 case PCI_CAP_ID_DBG:
1442 case PCI_CAP_ID_SSVID:
1443 show_ssvid(d, where);
1445 case PCI_CAP_ID_EXP:
1446 show_express(d, where, cap);
1447 can_have_ext_caps = 1;
1449 case PCI_CAP_ID_MSIX:
1450 show_msix(d, where, cap);
1453 printf("#%02x [%04x]\n", id, cap);
1458 if (can_have_ext_caps)
1463 show_htype0(struct device *d)
1466 show_rom(d, PCI_ROM_ADDRESS);
1471 show_htype1(struct device *d)
1473 u32 io_base = get_conf_byte(d, PCI_IO_BASE);
1474 u32 io_limit = get_conf_byte(d, PCI_IO_LIMIT);
1475 u32 io_type = io_base & PCI_IO_RANGE_TYPE_MASK;
1476 u32 mem_base = get_conf_word(d, PCI_MEMORY_BASE);
1477 u32 mem_limit = get_conf_word(d, PCI_MEMORY_LIMIT);
1478 u32 mem_type = mem_base & PCI_MEMORY_RANGE_TYPE_MASK;
1479 u32 pref_base = get_conf_word(d, PCI_PREF_MEMORY_BASE);
1480 u32 pref_limit = get_conf_word(d, PCI_PREF_MEMORY_LIMIT);
1481 u32 pref_type = pref_base & PCI_PREF_RANGE_TYPE_MASK;
1482 word sec_stat = get_conf_word(d, PCI_SEC_STATUS);
1483 word brc = get_conf_word(d, PCI_BRIDGE_CONTROL);
1484 int verb = verbose > 2;
1487 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1488 get_conf_byte(d, PCI_PRIMARY_BUS),
1489 get_conf_byte(d, PCI_SECONDARY_BUS),
1490 get_conf_byte(d, PCI_SUBORDINATE_BUS),
1491 get_conf_byte(d, PCI_SEC_LATENCY_TIMER));
1493 if (io_type != (io_limit & PCI_IO_RANGE_TYPE_MASK) ||
1494 (io_type != PCI_IO_RANGE_TYPE_16 && io_type != PCI_IO_RANGE_TYPE_32))
1495 printf("\t!!! Unknown I/O range types %x/%x\n", io_base, io_limit);
1498 io_base = (io_base & PCI_IO_RANGE_MASK) << 8;
1499 io_limit = (io_limit & PCI_IO_RANGE_MASK) << 8;
1500 if (io_type == PCI_IO_RANGE_TYPE_32)
1502 io_base |= (get_conf_word(d, PCI_IO_BASE_UPPER16) << 16);
1503 io_limit |= (get_conf_word(d, PCI_IO_LIMIT_UPPER16) << 16);
1505 if (io_base <= io_limit || verb)
1506 printf("\tI/O behind bridge: %08x-%08x\n", io_base, io_limit+0xfff);
1509 if (mem_type != (mem_limit & PCI_MEMORY_RANGE_TYPE_MASK) ||
1511 printf("\t!!! Unknown memory range types %x/%x\n", mem_base, mem_limit);
1514 mem_base = (mem_base & PCI_MEMORY_RANGE_MASK) << 16;
1515 mem_limit = (mem_limit & PCI_MEMORY_RANGE_MASK) << 16;
1516 if (mem_base <= mem_limit || verb)
1517 printf("\tMemory behind bridge: %08x-%08x\n", mem_base, mem_limit + 0xfffff);
1520 if (pref_type != (pref_limit & PCI_PREF_RANGE_TYPE_MASK) ||
1521 (pref_type != PCI_PREF_RANGE_TYPE_32 && pref_type != PCI_PREF_RANGE_TYPE_64))
1522 printf("\t!!! Unknown prefetchable memory range types %x/%x\n", pref_base, pref_limit);
1525 pref_base = (pref_base & PCI_PREF_RANGE_MASK) << 16;
1526 pref_limit = (pref_limit & PCI_PREF_RANGE_MASK) << 16;
1527 if (pref_base <= pref_limit || verb)
1529 if (pref_type == PCI_PREF_RANGE_TYPE_32)
1530 printf("\tPrefetchable memory behind bridge: %08x-%08x\n", pref_base, pref_limit + 0xfffff);
1532 printf("\tPrefetchable memory behind bridge: %08x%08x-%08x%08x\n",
1533 get_conf_long(d, PCI_PREF_BASE_UPPER32),
1535 get_conf_long(d, PCI_PREF_LIMIT_UPPER32),
1536 pref_limit + 0xfffff);
1541 printf("\tSecondary status: 66MHz%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c <SERR%c <PERR%c\n",
1542 FLAG(sec_stat, PCI_STATUS_66MHZ),
1543 FLAG(sec_stat, PCI_STATUS_FAST_BACK),
1544 FLAG(sec_stat, PCI_STATUS_PARITY),
1545 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1546 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1547 ((sec_stat & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1548 FLAG(sec_stat, PCI_STATUS_SIG_TARGET_ABORT),
1549 FLAG(sec_stat, PCI_STATUS_REC_TARGET_ABORT),
1550 FLAG(sec_stat, PCI_STATUS_REC_MASTER_ABORT),
1551 FLAG(sec_stat, PCI_STATUS_SIG_SYSTEM_ERROR),
1552 FLAG(sec_stat, PCI_STATUS_DETECTED_PARITY));
1554 show_rom(d, PCI_ROM_ADDRESS1);
1557 printf("\tBridgeCtl: Parity%c SERR%c NoISA%c VGA%c MAbort%c >Reset%c FastB2B%c\n",
1558 FLAG(brc, PCI_BRIDGE_CTL_PARITY),
1559 FLAG(brc, PCI_BRIDGE_CTL_SERR),
1560 FLAG(brc, PCI_BRIDGE_CTL_NO_ISA),
1561 FLAG(brc, PCI_BRIDGE_CTL_VGA),
1562 FLAG(brc, PCI_BRIDGE_CTL_MASTER_ABORT),
1563 FLAG(brc, PCI_BRIDGE_CTL_BUS_RESET),
1564 FLAG(brc, PCI_BRIDGE_CTL_FAST_BACK));
1570 show_htype2(struct device *d)
1573 word cmd = get_conf_word(d, PCI_COMMAND);
1574 word brc = get_conf_word(d, PCI_CB_BRIDGE_CONTROL);
1576 int verb = verbose > 2;
1579 printf("\tBus: primary=%02x, secondary=%02x, subordinate=%02x, sec-latency=%d\n",
1580 get_conf_byte(d, PCI_CB_PRIMARY_BUS),
1581 get_conf_byte(d, PCI_CB_CARD_BUS),
1582 get_conf_byte(d, PCI_CB_SUBORDINATE_BUS),
1583 get_conf_byte(d, PCI_CB_LATENCY_TIMER));
1587 u32 base = get_conf_long(d, PCI_CB_MEMORY_BASE_0 + p);
1588 u32 limit = get_conf_long(d, PCI_CB_MEMORY_LIMIT_0 + p);
1589 if (limit > base || verb)
1590 printf("\tMemory window %d: %08x-%08x%s%s\n", i, base, limit,
1591 (cmd & PCI_COMMAND_MEMORY) ? "" : " [disabled]",
1592 (brc & (PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 << i)) ? " (prefetchable)" : "");
1597 u32 base = get_conf_long(d, PCI_CB_IO_BASE_0 + p);
1598 u32 limit = get_conf_long(d, PCI_CB_IO_LIMIT_0 + p);
1599 if (!(base & PCI_IO_RANGE_TYPE_32))
1604 base &= PCI_CB_IO_RANGE_MASK;
1605 limit = (limit & PCI_CB_IO_RANGE_MASK) + 3;
1606 if (base <= limit || verb)
1607 printf("\tI/O window %d: %08x-%08x%s\n", i, base, limit,
1608 (cmd & PCI_COMMAND_IO) ? "" : " [disabled]");
1611 if (get_conf_word(d, PCI_CB_SEC_STATUS) & PCI_STATUS_SIG_SYSTEM_ERROR)
1612 printf("\tSecondary status: SERR\n");
1614 printf("\tBridgeCtl: Parity%c SERR%c ISA%c VGA%c MAbort%c >Reset%c 16bInt%c PostWrite%c\n",
1615 FLAG(brc, PCI_CB_BRIDGE_CTL_PARITY),
1616 FLAG(brc, PCI_CB_BRIDGE_CTL_SERR),
1617 FLAG(brc, PCI_CB_BRIDGE_CTL_ISA),
1618 FLAG(brc, PCI_CB_BRIDGE_CTL_VGA),
1619 FLAG(brc, PCI_CB_BRIDGE_CTL_MASTER_ABORT),
1620 FLAG(brc, PCI_CB_BRIDGE_CTL_CB_RESET),
1621 FLAG(brc, PCI_CB_BRIDGE_CTL_16BIT_INT),
1622 FLAG(brc, PCI_CB_BRIDGE_CTL_POST_WRITES));
1624 if (d->config_cached < 128)
1626 printf("\t<access denied to the rest>\n");
1630 exca = get_conf_word(d, PCI_CB_LEGACY_MODE_BASE);
1632 printf("\t16-bit legacy interface ports at %04x\n", exca);
1636 show_verbose(struct device *d)
1638 struct pci_dev *p = d->dev;
1639 word status = get_conf_word(d, PCI_STATUS);
1640 word cmd = get_conf_word(d, PCI_COMMAND);
1641 word class = p->device_class;
1642 byte bist = get_conf_byte(d, PCI_BIST);
1643 byte htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1644 byte latency = get_conf_byte(d, PCI_LATENCY_TIMER);
1645 byte cache_line = get_conf_byte(d, PCI_CACHE_LINE_SIZE);
1646 byte max_lat, min_gnt;
1647 byte int_pin = get_conf_byte(d, PCI_INTERRUPT_PIN);
1648 unsigned int irq = p->irq;
1649 word subsys_v = 0, subsys_d = 0;
1650 char ssnamebuf[256];
1656 case PCI_HEADER_TYPE_NORMAL:
1657 if (class == PCI_CLASS_BRIDGE_PCI)
1658 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1659 max_lat = get_conf_byte(d, PCI_MAX_LAT);
1660 min_gnt = get_conf_byte(d, PCI_MIN_GNT);
1661 subsys_v = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1662 subsys_d = get_conf_word(d, PCI_SUBSYSTEM_ID);
1664 case PCI_HEADER_TYPE_BRIDGE:
1665 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1666 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1667 irq = int_pin = min_gnt = max_lat = 0;
1669 case PCI_HEADER_TYPE_CARDBUS:
1670 if ((class >> 8) != PCI_BASE_CLASS_BRIDGE)
1671 printf("\t!!! Invalid class %04x for header type %02x\n", class, htype);
1672 min_gnt = max_lat = 0;
1673 if (d->config_cached >= 128)
1675 subsys_v = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1676 subsys_d = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1680 printf("\t!!! Unknown header type %02x\n", htype);
1684 if (subsys_v && subsys_v != 0xffff)
1685 printf("\tSubsystem: %s\n",
1686 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1687 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1688 p->vendor_id, p->device_id, subsys_v, subsys_d));
1692 printf("\tControl: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c\n",
1693 FLAG(cmd, PCI_COMMAND_IO),
1694 FLAG(cmd, PCI_COMMAND_MEMORY),
1695 FLAG(cmd, PCI_COMMAND_MASTER),
1696 FLAG(cmd, PCI_COMMAND_SPECIAL),
1697 FLAG(cmd, PCI_COMMAND_INVALIDATE),
1698 FLAG(cmd, PCI_COMMAND_VGA_PALETTE),
1699 FLAG(cmd, PCI_COMMAND_PARITY),
1700 FLAG(cmd, PCI_COMMAND_WAIT),
1701 FLAG(cmd, PCI_COMMAND_SERR),
1702 FLAG(cmd, PCI_COMMAND_FAST_BACK));
1703 printf("\tStatus: Cap%c 66MHz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c\n",
1704 FLAG(status, PCI_STATUS_CAP_LIST),
1705 FLAG(status, PCI_STATUS_66MHZ),
1706 FLAG(status, PCI_STATUS_UDF),
1707 FLAG(status, PCI_STATUS_FAST_BACK),
1708 FLAG(status, PCI_STATUS_PARITY),
1709 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1710 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1711 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??",
1712 FLAG(status, PCI_STATUS_SIG_TARGET_ABORT),
1713 FLAG(status, PCI_STATUS_REC_TARGET_ABORT),
1714 FLAG(status, PCI_STATUS_REC_MASTER_ABORT),
1715 FLAG(status, PCI_STATUS_SIG_SYSTEM_ERROR),
1716 FLAG(status, PCI_STATUS_DETECTED_PARITY));
1717 if (cmd & PCI_COMMAND_MASTER)
1719 printf("\tLatency: %d", latency);
1720 if (min_gnt || max_lat)
1724 printf("%dns min", min_gnt*250);
1725 if (min_gnt && max_lat)
1728 printf("%dns max", max_lat*250);
1732 printf(", Cache Line Size: %d bytes", cache_line * 4);
1736 printf("\tInterrupt: pin %c routed to IRQ " PCIIRQ_FMT "\n",
1737 (int_pin ? 'A' + int_pin - 1 : '?'), irq);
1741 printf("\tFlags: ");
1742 if (cmd & PCI_COMMAND_MASTER)
1743 printf("bus master, ");
1744 if (cmd & PCI_COMMAND_VGA_PALETTE)
1745 printf("VGA palette snoop, ");
1746 if (cmd & PCI_COMMAND_WAIT)
1747 printf("stepping, ");
1748 if (cmd & PCI_COMMAND_FAST_BACK)
1749 printf("fast Back2Back, ");
1750 if (status & PCI_STATUS_66MHZ)
1752 if (status & PCI_STATUS_UDF)
1753 printf("user-definable features, ");
1755 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_SLOW) ? "slow" :
1756 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_MEDIUM) ? "medium" :
1757 ((status & PCI_STATUS_DEVSEL_MASK) == PCI_STATUS_DEVSEL_FAST) ? "fast" : "??");
1758 if (cmd & PCI_COMMAND_MASTER)
1759 printf(", latency %d", latency);
1761 printf(", IRQ " PCIIRQ_FMT, irq);
1765 if (bist & PCI_BIST_CAPABLE)
1767 if (bist & PCI_BIST_START)
1768 printf("\tBIST is running\n");
1770 printf("\tBIST result: %02x\n", bist & PCI_BIST_CODE_MASK);
1775 case PCI_HEADER_TYPE_NORMAL:
1778 case PCI_HEADER_TYPE_BRIDGE:
1781 case PCI_HEADER_TYPE_CARDBUS:
1788 show_hex_dump(struct device *d)
1790 unsigned int i, cnt;
1792 cnt = d->config_cached;
1793 if (show_hex >= 3 && config_fetch(d, cnt, 256-cnt))
1796 if (show_hex >= 4 && config_fetch(d, 256, 4096-256))
1800 for(i=0; i<cnt; i++)
1804 printf(" %02x", get_conf_byte(d, i));
1811 print_shell_escaped(char *c)
1816 if (*c == '"' || *c == '\\')
1824 show_machine(struct device *d)
1826 struct pci_dev *p = d->dev;
1828 word sv_id=0, sd_id=0;
1829 char classbuf[128], vendbuf[128], devbuf[128], svbuf[128], sdbuf[128];
1831 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
1833 case PCI_HEADER_TYPE_NORMAL:
1834 sv_id = get_conf_word(d, PCI_SUBSYSTEM_VENDOR_ID);
1835 sd_id = get_conf_word(d, PCI_SUBSYSTEM_ID);
1837 case PCI_HEADER_TYPE_CARDBUS:
1838 if (d->config_cached >= 128)
1840 sv_id = get_conf_word(d, PCI_CB_SUBSYSTEM_VENDOR_ID);
1841 sd_id = get_conf_word(d, PCI_CB_SUBSYSTEM_ID);
1848 printf((machine_readable >= 2) ? "Slot:\t" : "Device:\t");
1851 printf("Class:\t%s\n",
1852 pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, p->device_class));
1853 printf("Vendor:\t%s\n",
1854 pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id));
1855 printf("Device:\t%s\n",
1856 pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id));
1857 if (sv_id && sv_id != 0xffff)
1859 printf("SVendor:\t%s\n",
1860 pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, sv_id));
1861 printf("SDevice:\t%s\n",
1862 pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
1864 if (c = get_conf_byte(d, PCI_REVISION_ID))
1865 printf("Rev:\t%02x\n", c);
1866 if (c = get_conf_byte(d, PCI_CLASS_PROG))
1867 printf("ProgIf:\t%02x\n", c);
1872 print_shell_escaped(pci_lookup_name(pacc, classbuf, sizeof(classbuf), PCI_LOOKUP_CLASS, p->device_class));
1873 print_shell_escaped(pci_lookup_name(pacc, vendbuf, sizeof(vendbuf), PCI_LOOKUP_VENDOR, p->vendor_id, p->device_id));
1874 print_shell_escaped(pci_lookup_name(pacc, devbuf, sizeof(devbuf), PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id));
1875 if (c = get_conf_byte(d, PCI_REVISION_ID))
1876 printf(" -r%02x", c);
1877 if (c = get_conf_byte(d, PCI_CLASS_PROG))
1878 printf(" -p%02x", c);
1879 if (sv_id && sv_id != 0xffff)
1881 print_shell_escaped(pci_lookup_name(pacc, svbuf, sizeof(svbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR, sv_id));
1882 print_shell_escaped(pci_lookup_name(pacc, sdbuf, sizeof(sdbuf), PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE, p->vendor_id, p->device_id, sv_id, sd_id));
1885 printf(" \"\" \"\"");
1891 show_device(struct device *d)
1893 if (machine_readable)
1901 if (verbose || show_hex)
1910 for(d=first_dev; d; d=d->next)
1917 struct bridge *chain; /* Single-linked list of bridges */
1918 struct bridge *next, *child; /* Tree of bridges */
1919 struct bus *first_bus; /* List of buses connected to this bridge */
1920 unsigned int domain;
1921 unsigned int primary, secondary, subordinate; /* Bus numbers */
1922 struct device *br_dev;
1926 unsigned int domain;
1927 unsigned int number;
1928 struct bus *sibling;
1929 struct device *first_dev, **last_dev;
1932 static struct bridge host_bridge = { NULL, NULL, NULL, NULL, 0, ~0, 0, ~0, NULL };
1935 find_bus(struct bridge *b, unsigned int domain, unsigned int n)
1939 for(bus=b->first_bus; bus; bus=bus->sibling)
1940 if (bus->domain == domain && bus->number == n)
1946 new_bus(struct bridge *b, unsigned int domain, unsigned int n)
1948 struct bus *bus = xmalloc(sizeof(struct bus));
1949 bus->domain = domain;
1951 bus->sibling = b->first_bus;
1952 bus->first_dev = NULL;
1953 bus->last_dev = &bus->first_dev;
1959 insert_dev(struct device *d, struct bridge *b)
1961 struct pci_dev *p = d->dev;
1964 if (! (bus = find_bus(b, p->domain, p->bus)))
1967 for(c=b->child; c; c=c->next)
1968 if (c->domain == p->domain && c->secondary <= p->bus && p->bus <= c->subordinate)
1973 bus = new_bus(b, p->domain, p->bus);
1975 /* Simple insertion at the end _does_ guarantee the correct order as the
1976 * original device list was sorted by (domain, bus, devfn) lexicographically
1977 * and all devices on the new list have the same bus number.
1980 bus->last_dev = &d->next;
1987 struct device *d, *d2;
1988 struct bridge **last_br, *b;
1990 /* Build list of bridges */
1992 last_br = &host_bridge.chain;
1993 for(d=first_dev; d; d=d->next)
1995 word class = d->dev->device_class;
1996 byte ht = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1997 if (class == PCI_CLASS_BRIDGE_PCI &&
1998 (ht == PCI_HEADER_TYPE_BRIDGE || ht == PCI_HEADER_TYPE_CARDBUS))
2000 b = xmalloc(sizeof(struct bridge));
2001 b->domain = d->dev->domain;
2002 if (ht == PCI_HEADER_TYPE_BRIDGE)
2004 b->primary = get_conf_byte(d, PCI_CB_PRIMARY_BUS);
2005 b->secondary = get_conf_byte(d, PCI_CB_CARD_BUS);
2006 b->subordinate = get_conf_byte(d, PCI_CB_SUBORDINATE_BUS);
2010 b->primary = get_conf_byte(d, PCI_PRIMARY_BUS);
2011 b->secondary = get_conf_byte(d, PCI_SECONDARY_BUS);
2012 b->subordinate = get_conf_byte(d, PCI_SUBORDINATE_BUS);
2015 last_br = &b->chain;
2016 b->next = b->child = NULL;
2017 b->first_bus = NULL;
2023 /* Create a bridge tree */
2025 for(b=&host_bridge; b; b=b->chain)
2027 struct bridge *c, *best;
2029 for(c=&host_bridge; c; c=c->chain)
2030 if (c != b && (c == &host_bridge || b->domain == c->domain) &&
2031 b->primary >= c->secondary && b->primary <= c->subordinate &&
2032 (!best || best->subordinate - best->primary > c->subordinate - c->primary))
2036 b->next = best->child;
2041 /* Insert secondary bus for each bridge */
2043 for(b=&host_bridge; b; b=b->chain)
2044 if (!find_bus(b, b->domain, b->secondary))
2045 new_bus(b, b->domain, b->secondary);
2047 /* Create bus structs and link devices */
2049 for(d=first_dev; d;)
2052 insert_dev(d, &host_bridge);
2058 print_it(char *line, char *p)
2062 fputs(line, stdout);
2063 for(p=line; *p; p++)
2064 if (*p == '+' || *p == '|')
2070 static void show_tree_bridge(struct bridge *, char *, char *);
2073 show_tree_dev(struct device *d, char *line, char *p)
2075 struct pci_dev *q = d->dev;
2079 p += sprintf(p, "%02x.%x", q->dev, q->func);
2080 for(b=&host_bridge; b; b=b->chain)
2083 if (b->secondary == b->subordinate)
2084 p += sprintf(p, "-[%04x:%02x]-", b->domain, b->secondary);
2086 p += sprintf(p, "-[%04x:%02x-%02x]-", b->domain, b->secondary, b->subordinate);
2087 show_tree_bridge(b, line, p);
2091 p += sprintf(p, " %s",
2092 pci_lookup_name(pacc, namebuf, sizeof(namebuf),
2093 PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
2094 q->vendor_id, q->device_id));
2099 show_tree_bus(struct bus *b, char *line, char *p)
2103 else if (!b->first_dev->next)
2107 show_tree_dev(b->first_dev, line, p);
2111 struct device *d = b->first_dev;
2116 show_tree_dev(d, line, p+2);
2121 show_tree_dev(d, line, p+2);
2126 show_tree_bridge(struct bridge *b, char *line, char *p)
2129 if (!b->first_bus->sibling)
2131 if (b == &host_bridge)
2132 p += sprintf(p, "[%04x:%02x]-", b->domain, b->first_bus->number);
2133 show_tree_bus(b->first_bus, line, p);
2137 struct bus *u = b->first_bus;
2142 k = p + sprintf(p, "+-[%04x:%02x]-", u->domain, u->number);
2143 show_tree_bus(u, line, k);
2146 k = p + sprintf(p, "\\-[%04x:%02x]-", u->domain, u->number);
2147 show_tree_bus(u, line, k);
2157 show_tree_bridge(&host_bridge, line, line);
2160 /* Bus mapping mode */
2163 struct bus_bridge *next;
2164 byte this, dev, func, first, last, bug;
2170 struct bus_bridge *bridges, *via;
2173 static struct bus_info *bus_info;
2176 map_bridge(struct bus_info *bi, struct device *d, int np, int ns, int nl)
2178 struct bus_bridge *b = xmalloc(sizeof(struct bus_bridge));
2179 struct pci_dev *p = d->dev;
2181 b->next = bi->bridges;
2183 b->this = get_conf_byte(d, np);
2186 b->first = get_conf_byte(d, ns);
2187 b->last = get_conf_byte(d, nl);
2188 printf("## %02x.%02x:%d is a bridge from %02x to %02x-%02x\n",
2189 p->bus, p->dev, p->func, b->this, b->first, b->last);
2190 if (b->this != p->bus)
2191 printf("!!! Bridge points to invalid primary bus.\n");
2192 if (b->first > b->last)
2194 printf("!!! Bridge points to invalid bus range.\n");
2203 int verbose = pacc->debugging;
2204 struct bus_info *bi = bus_info + bus;
2208 printf("Mapping bus %02x\n", bus);
2209 for(dev = 0; dev < 32; dev++)
2210 if (filter.slot < 0 || filter.slot == dev)
2213 for(func = 0; func < func_limit; func++)
2214 if (filter.func < 0 || filter.func == func)
2216 /* XXX: Bus mapping supports only domain 0 */
2217 struct pci_dev *p = pci_get_dev(pacc, 0, bus, dev, func);
2218 u16 vendor = pci_read_word(p, PCI_VENDOR_ID);
2219 if (vendor && vendor != 0xffff)
2221 if (!func && (pci_read_byte(p, PCI_HEADER_TYPE) & 0x80))
2224 printf("Discovered device %02x:%02x.%d\n", bus, dev, func);
2226 if (d = scan_device(p))
2229 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
2231 case PCI_HEADER_TYPE_BRIDGE:
2232 map_bridge(bi, d, PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS);
2234 case PCI_HEADER_TYPE_CARDBUS:
2235 map_bridge(bi, d, PCI_CB_PRIMARY_BUS, PCI_CB_CARD_BUS, PCI_CB_SUBORDINATE_BUS);
2241 printf("But it was filtered out.\n");
2249 do_map_bridges(int bus, int min, int max)
2251 struct bus_info *bi = bus_info + bus;
2252 struct bus_bridge *b;
2255 for(b=bi->bridges; b; b=b->next)
2257 if (bus_info[b->first].guestbook)
2259 else if (b->first < min || b->last > max)
2263 bus_info[b->first].via = b;
2264 do_map_bridges(b->first, b->first, b->last);
2274 printf("\nSummary of buses:\n\n");
2275 for(i=0; i<256; i++)
2276 if (bus_info[i].exists && !bus_info[i].guestbook)
2277 do_map_bridges(i, 0, 255);
2278 for(i=0; i<256; i++)
2280 struct bus_info *bi = bus_info + i;
2281 struct bus_bridge *b = bi->via;
2285 printf("%02x: ", i);
2287 printf("Entered via %02x:%02x.%d\n", b->this, b->dev, b->func);
2289 printf("Primary host bus\n");
2291 printf("Secondary host bus (?)\n");
2293 for(b=bi->bridges; b; b=b->next)
2295 printf("\t%02x.%d Bridge to %02x-%02x", b->dev, b->func, b->first, b->last);
2299 printf(" <overlap bug>");
2302 printf(" <crossing bug>");
2313 if (pacc->method == PCI_ACCESS_PROC_BUS_PCI ||
2314 pacc->method == PCI_ACCESS_DUMP)
2315 printf("WARNING: Bus mapping can be reliable only with direct hardware access enabled.\n\n");
2316 bus_info = xmalloc(sizeof(struct bus_info) * 256);
2317 bzero(bus_info, sizeof(struct bus_info) * 256);
2318 if (filter.bus >= 0)
2319 do_map_bus(filter.bus);
2323 for(bus=0; bus<256; bus++)
2332 main(int argc, char **argv)
2337 if (argc == 2 && !strcmp(argv[1], "--version"))
2339 puts("lspci version " PCIUTILS_VERSION);
2345 pci_filter_init(pacc, &filter);
2347 while ((i = getopt(argc, argv, options)) != -1)
2351 pacc->numeric_ids++;
2357 pacc->buscentric = 1;
2358 buscentric_view = 1;
2361 if (msg = pci_filter_parse_slot(&filter, optarg))
2365 if (msg = pci_filter_parse_id(&filter, optarg))
2375 pci_set_name_list_path(pacc, optarg, 0);
2387 if (parse_generic_option(i, pacc, optarg))
2390 fprintf(stderr, help_msg, pacc->id_file_name);
2410 return (seen_errors ? 2 : 0);