2 * The PCI Utilities -- Show Extended Capabilities
4 * Copyright (c) 1997--2010 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL.
15 cap_tph(struct device *d, int where)
18 printf("Transaction Processing Hints\n");
22 if (!config_fetch(d, where + PCI_TPH_CAPABILITIES, 4))
25 tph_cap = get_conf_long(d, where + PCI_TPH_CAPABILITIES);
27 if (tph_cap & PCI_TPH_INTVEC_SUP)
28 printf("\t\tInterrupt vector mode supported\n");
29 if (tph_cap & PCI_TPH_DEV_SUP)
30 printf("\t\tDevice specific mode supported\n");
31 if (tph_cap & PCI_TPH_EXT_REQ_SUP)
32 printf("\t\tExtended requester support\n");
34 switch (tph_cap & PCI_TPH_ST_LOC_MASK) {
36 printf("\t\tNo steering table available\n");
39 printf("\t\tSteering table in TPH capability structure\n");
42 printf("\t\tSteering table in MSI-X table\n");
45 printf("\t\tReserved steering table location\n");
51 cap_ltr_scale(u8 scale)
53 return 1 << (scale * 5);
57 cap_ltr(struct device *d, int where)
61 printf("Latency Tolerance Reporting\n");
65 if (!config_fetch(d, where + PCI_LTR_MAX_SNOOP, 4))
68 snoop = get_conf_word(d, where + PCI_LTR_MAX_SNOOP);
69 scale = cap_ltr_scale((snoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK);
70 printf("\t\tMax snoop latency: %lldns\n",
71 ((unsigned long long)snoop & PCI_LTR_VALUE_MASK) * scale);
73 nosnoop = get_conf_word(d, where + PCI_LTR_MAX_NOSNOOP);
74 scale = cap_ltr_scale((nosnoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK);
75 printf("\t\tMax no snoop latency: %lldns\n",
76 ((unsigned long long)nosnoop & PCI_LTR_VALUE_MASK) * scale);
80 cap_dsn(struct device *d, int where)
83 if (!config_fetch(d, where + 4, 8))
85 t1 = get_conf_long(d, where + 4);
86 t2 = get_conf_long(d, where + 8);
87 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
88 t2 >> 24, (t2 >> 16) & 0xff, (t2 >> 8) & 0xff, t2 & 0xff,
89 t1 >> 24, (t1 >> 16) & 0xff, (t1 >> 8) & 0xff, t1 & 0xff);
93 cap_aer(struct device *d, int where)
97 printf("Advanced Error Reporting\n");
101 if (!config_fetch(d, where + PCI_ERR_UNCOR_STATUS, 24))
104 l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS);
105 printf("\t\tUESta:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
106 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
107 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
108 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
109 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
110 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
111 l = get_conf_long(d, where + PCI_ERR_UNCOR_MASK);
112 printf("\t\tUEMsk:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
113 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
114 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
115 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
116 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
117 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
118 l = get_conf_long(d, where + PCI_ERR_UNCOR_SEVER);
119 printf("\t\tUESvrt:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
120 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
121 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
122 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
123 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
124 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
125 l = get_conf_long(d, where + PCI_ERR_COR_STATUS);
126 printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c\n",
127 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
128 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
129 l = get_conf_long(d, where + PCI_ERR_COR_MASK);
130 printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c\n",
131 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
132 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
133 l = get_conf_long(d, where + PCI_ERR_CAP);
134 printf("\t\tAERCap:\tFirst Error Pointer: %02x, GenCap%c CGenEn%c ChkCap%c ChkEn%c\n",
135 PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE),
136 FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE));
140 static void cap_dpc(struct device *d, int where)
144 printf("Downstream Port Containment\n");
148 if (!config_fetch(d, where + PCI_DPC_CAP, 8))
151 l = get_conf_word(d, where + PCI_DPC_CAP);
152 printf("\t\tDpcCap:\tINT Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
153 PCI_DPC_CAP_INT_MSG(l), FLAG(l, PCI_DPC_CAP_RP_EXT), FLAG(l, PCI_DPC_CAP_TLP_BLOCK),
154 FLAG(l, PCI_DPC_CAP_SW_TRIGGER), PCI_DPC_CAP_RP_LOG(l), FLAG(l, PCI_DPC_CAP_DL_ACT_ERR));
156 l = get_conf_word(d, where + PCI_DPC_CTL);
157 printf("\t\tDpcCtl:\tTrigger:%x Cmpl%c INT%c ErrCor%c PoisonedTLP%c SwTrigger%c DL_ActiveErr%c\n",
158 PCI_DPC_CTL_TRIGGER(l), FLAG(l, PCI_DPC_CTL_CMPL), FLAG(l, PCI_DPC_CTL_INT),
159 FLAG(l, PCI_DPC_CTL_ERR_COR), FLAG(l, PCI_DPC_CTL_TLP), FLAG(l, PCI_DPC_CTL_SW_TRIGGER),
160 FLAG(l, PCI_DPC_CTL_DL_ACTIVE));
162 l = get_conf_word(d, where + PCI_DPC_STATUS);
163 printf("\t\tDpcSta:\tTrigger%c Reason:%02x INT%c RPBusy%c TriggerExt:%02x RP PIO ErrPtr:%02x\n",
164 FLAG(l, PCI_DPC_STS_TRIGGER), PCI_DPC_STS_REASON(l), FLAG(l, PCI_DPC_STS_INT),
165 FLAG(l, PCI_DPC_STS_RP_BUSY), PCI_DPC_STS_TRIGGER_EXT(l), PCI_DPC_STS_PIO_FEP(l));
167 l = get_conf_word(d, where + PCI_DPC_SOURCE);
168 printf("\t\tSource:\t%04x\n", l);
172 cap_acs(struct device *d, int where)
176 printf("Access Control Services\n");
180 if (!config_fetch(d, where + PCI_ACS_CAP, 4))
183 w = get_conf_word(d, where + PCI_ACS_CAP);
184 printf("\t\tACSCap:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
186 FLAG(w, PCI_ACS_CAP_VALID), FLAG(w, PCI_ACS_CAP_BLOCK), FLAG(w, PCI_ACS_CAP_REQ_RED),
187 FLAG(w, PCI_ACS_CAP_CMPLT_RED), FLAG(w, PCI_ACS_CAP_FORWARD), FLAG(w, PCI_ACS_CAP_EGRESS),
188 FLAG(w, PCI_ACS_CAP_TRANS));
189 w = get_conf_word(d, where + PCI_ACS_CTRL);
190 printf("\t\tACSCtl:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
192 FLAG(w, PCI_ACS_CTRL_VALID), FLAG(w, PCI_ACS_CTRL_BLOCK), FLAG(w, PCI_ACS_CTRL_REQ_RED),
193 FLAG(w, PCI_ACS_CTRL_CMPLT_RED), FLAG(w, PCI_ACS_CTRL_FORWARD), FLAG(w, PCI_ACS_CTRL_EGRESS),
194 FLAG(w, PCI_ACS_CTRL_TRANS));
198 cap_ari(struct device *d, int where)
202 printf("Alternative Routing-ID Interpretation (ARI)\n");
206 if (!config_fetch(d, where + PCI_ARI_CAP, 4))
209 w = get_conf_word(d, where + PCI_ARI_CAP);
210 printf("\t\tARICap:\tMFVC%c ACS%c, Next Function: %d\n",
211 FLAG(w, PCI_ARI_CAP_MFVC), FLAG(w, PCI_ARI_CAP_ACS),
213 w = get_conf_word(d, where + PCI_ARI_CTRL);
214 printf("\t\tARICtl:\tMFVC%c ACS%c, Function Group: %d\n",
215 FLAG(w, PCI_ARI_CTRL_MFVC), FLAG(w, PCI_ARI_CTRL_ACS),
220 cap_ats(struct device *d, int where)
224 printf("Address Translation Service (ATS)\n");
228 if (!config_fetch(d, where + PCI_ATS_CAP, 4))
231 w = get_conf_word(d, where + PCI_ATS_CAP);
232 printf("\t\tATSCap:\tInvalidate Queue Depth: %02x\n", PCI_ATS_CAP_IQD(w));
233 w = get_conf_word(d, where + PCI_ATS_CTRL);
234 printf("\t\tATSCtl:\tEnable%c, Smallest Translation Unit: %02x\n",
235 FLAG(w, PCI_ATS_CTRL_ENABLE), PCI_ATS_CTRL_STU(w));
239 cap_pri(struct device *d, int where)
244 printf("Page Request Interface (PRI)\n");
248 if (!config_fetch(d, where + PCI_PRI_CTRL, 0xc))
251 w = get_conf_word(d, where + PCI_PRI_CTRL);
252 printf("\t\tPRICtl: Enable%c Reset%c\n",
253 FLAG(w, PCI_PRI_CTRL_ENABLE), FLAG(w, PCI_PRI_CTRL_RESET));
254 w = get_conf_word(d, where + PCI_PRI_STATUS);
255 printf("\t\tPRISta: RF%c UPRGI%c Stopped%c\n",
256 FLAG(w, PCI_PRI_STATUS_RF), FLAG(w, PCI_PRI_STATUS_UPRGI),
257 FLAG(w, PCI_PRI_STATUS_STOPPED));
258 l = get_conf_long(d, where + PCI_PRI_MAX_REQ);
259 printf("\t\tPage Request Capacity: %08x, ", l);
260 l = get_conf_long(d, where + PCI_PRI_ALLOC_REQ);
261 printf("Page Request Allocation: %08x\n", l);
265 cap_pasid(struct device *d, int where)
269 printf("Process Address Space ID (PASID)\n");
273 if (!config_fetch(d, where + PCI_PASID_CAP, 4))
276 w = get_conf_word(d, where + PCI_PASID_CAP);
277 printf("\t\tPASIDCap: Exec%c Priv%c, Max PASID Width: %02x\n",
278 FLAG(w, PCI_PASID_CAP_EXEC), FLAG(w, PCI_PASID_CAP_PRIV),
279 PCI_PASID_CAP_WIDTH(w));
280 w = get_conf_word(d, where + PCI_PASID_CTRL);
281 printf("\t\tPASIDCtl: Enable%c Exec%c Priv%c\n",
282 FLAG(w, PCI_PASID_CTRL_ENABLE), FLAG(w, PCI_PASID_CTRL_EXEC),
283 FLAG(w, PCI_PASID_CTRL_PRIV));
287 cap_sriov(struct device *d, int where)
294 printf("Single Root I/O Virtualization (SR-IOV)\n");
298 if (!config_fetch(d, where + PCI_IOV_CAP, 0x3c))
301 l = get_conf_long(d, where + PCI_IOV_CAP);
302 printf("\t\tIOVCap:\tMigration%c, Interrupt Message Number: %03x\n",
303 FLAG(l, PCI_IOV_CAP_VFM), PCI_IOV_CAP_IMN(l));
304 w = get_conf_word(d, where + PCI_IOV_CTRL);
305 printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c\n",
306 FLAG(w, PCI_IOV_CTRL_VFE), FLAG(w, PCI_IOV_CTRL_VFME),
307 FLAG(w, PCI_IOV_CTRL_VFMIE), FLAG(w, PCI_IOV_CTRL_MSE),
308 FLAG(w, PCI_IOV_CTRL_ARI));
309 w = get_conf_word(d, where + PCI_IOV_STATUS);
310 printf("\t\tIOVSta:\tMigration%c\n", FLAG(w, PCI_IOV_STATUS_MS));
311 w = get_conf_word(d, where + PCI_IOV_INITIALVF);
312 printf("\t\tInitial VFs: %d, ", w);
313 w = get_conf_word(d, where + PCI_IOV_TOTALVF);
314 printf("Total VFs: %d, ", w);
315 w = get_conf_word(d, where + PCI_IOV_NUMVF);
316 printf("Number of VFs: %d, ", w);
317 b = get_conf_byte(d, where + PCI_IOV_FDL);
318 printf("Function Dependency Link: %02x\n", b);
319 w = get_conf_word(d, where + PCI_IOV_OFFSET);
320 printf("\t\tVF offset: %d, ", w);
321 w = get_conf_word(d, where + PCI_IOV_STRIDE);
322 printf("stride: %d, ", w);
323 w = get_conf_word(d, where + PCI_IOV_DID);
324 printf("Device ID: %04x\n", w);
325 l = get_conf_long(d, where + PCI_IOV_SUPPS);
326 printf("\t\tSupported Page Size: %08x, ", l);
327 l = get_conf_long(d, where + PCI_IOV_SYSPS);
328 printf("System Page Size: %08x\n", l);
330 for (i=0; i < PCI_IOV_NUM_BAR; i++)
335 l = get_conf_long(d, where + PCI_IOV_BAR_BASE + 4*i);
340 printf("\t\tRegion %d: Memory at ", i);
341 addr = l & PCI_ADDR_MEM_MASK;
342 type = l & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
343 if (type == PCI_BASE_ADDRESS_MEM_TYPE_64)
346 h = get_conf_long(d, where + PCI_IOV_BAR_BASE + (i*4));
349 printf("%08x (%s-bit, %sprefetchable)\n",
351 (type == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32" : "64",
352 (l & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
355 l = get_conf_long(d, where + PCI_IOV_MSAO);
356 printf("\t\tVF Migration: offset: %08x, BIR: %x\n", PCI_IOV_MSA_OFFSET(l),
361 cap_vc(struct device *d, int where)
368 static const char ref_clocks[][6] = { "100ns" };
369 static const char arb_selects[8][7] = { "Fixed", "WRR32", "WRR64", "WRR128", "??4", "??5", "??6", "??7" };
370 static const char vc_arb_selects[8][8] = { "Fixed", "WRR32", "WRR64", "WRR128", "TWRR128", "WRR256", "??6", "??7" };
373 printf("Virtual Channel\n");
377 if (!config_fetch(d, where + 4, 0x1c - 4))
380 cr1 = get_conf_long(d, where + PCI_VC_PORT_REG1);
381 cr2 = get_conf_long(d, where + PCI_VC_PORT_REG2);
382 ctrl = get_conf_word(d, where + PCI_VC_PORT_CTRL);
383 status = get_conf_word(d, where + PCI_VC_PORT_STATUS);
385 evc_cnt = BITS(cr1, 0, 3);
386 printf("\t\tCaps:\tLPEVC=%d RefClk=%s PATEntryBits=%d\n",
388 TABLE(ref_clocks, BITS(cr1, 8, 2), buf),
389 1 << BITS(cr1, 10, 2));
393 if (arb_selects[i][0] != '?' || cr2 & (1 << i))
394 printf("%c%s%c", (i ? ' ' : '\t'), arb_selects[i], FLAG(cr2, 1 << i));
395 arb_table_pos = BITS(cr2, 24, 8);
397 printf("\n\t\tCtrl:\tArbSelect=%s\n", TABLE(arb_selects, BITS(ctrl, 1, 3), buf));
398 printf("\t\tStatus:\tInProgress%c\n", FLAG(status, 1));
402 arb_table_pos = where + 16*arb_table_pos;
403 printf("\t\tPort Arbitration Table [%x] <?>\n", arb_table_pos);
406 for (i=0; i<=evc_cnt; i++)
408 int pos = where + PCI_VC_RES_CAP + 12*i;
413 printf("\t\tVC%d:\t", i);
414 if (!config_fetch(d, pos, 12))
416 printf("<unreadable>\n");
419 rcap = get_conf_long(d, pos);
420 rctrl = get_conf_long(d, pos+4);
421 rstatus = get_conf_word(d, pos+10);
423 pat_pos = BITS(rcap, 24, 8);
424 printf("Caps:\tPATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c\n",
426 BITS(rcap, 16, 6) + 1,
427 FLAG(rcap, 1 << 15));
429 printf("\t\t\tArb:");
431 if (vc_arb_selects[j][0] != '?' || rcap & (1 << j))
432 printf("%c%s%c", (j ? ' ' : '\t'), vc_arb_selects[j], FLAG(rcap, 1 << j));
434 printf("\n\t\t\tCtrl:\tEnable%c ID=%d ArbSelect=%s TC/VC=%02x\n",
435 FLAG(rctrl, 1 << 31),
437 TABLE(vc_arb_selects, BITS(rctrl, 17, 3), buf),
440 printf("\t\t\tStatus:\tNegoPending%c InProgress%c\n",
445 printf("\t\t\tPort Arbitration Table <?>\n");
450 cap_rclink(struct device *d, int where)
455 static const char elt_types[][9] = { "Config", "Egress", "Internal" };
458 printf("Root Complex Link\n");
462 if (!config_fetch(d, where + 4, PCI_RCLINK_LINK1 - 4))
465 esd = get_conf_long(d, where + PCI_RCLINK_ESD);
466 num_links = BITS(esd, 8, 8);
467 printf("\t\tDesc:\tPortNumber=%02x ComponentID=%02x EltType=%s\n",
470 TABLE(elt_types, BITS(esd, 0, 8), buf));
472 for (i=0; i<num_links; i++)
474 int pos = where + PCI_RCLINK_LINK1 + i*PCI_RCLINK_LINK_SIZE;
476 u32 addr_lo, addr_hi;
478 printf("\t\tLink%d:\t", i);
479 if (!config_fetch(d, pos, PCI_RCLINK_LINK_SIZE))
481 printf("<unreadable>\n");
484 desc = get_conf_long(d, pos + PCI_RCLINK_LINK_DESC);
485 addr_lo = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR);
486 addr_hi = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR + 4);
488 printf("Desc:\tTargetPort=%02x TargetComponent=%02x AssocRCRB%c LinkType=%s LinkValid%c\n",
492 ((desc & 2) ? "Config" : "MemMapped"),
500 printf("\t\t\tAddr:\t%02x:%02x.%d CfgSpace=%08x%08x\n",
501 BITS(addr_lo, 20, n),
502 BITS(addr_lo, 15, 5),
503 BITS(addr_lo, 12, 3),
507 printf("\t\t\tAddr:\t%08x%08x\n", addr_hi, addr_lo);
512 cap_evendor(struct device *d, int where)
516 printf("Vendor Specific Information: ");
517 if (!config_fetch(d, where + PCI_EVNDR_HEADER, 4))
519 printf("<unreadable>\n");
523 hdr = get_conf_long(d, where + PCI_EVNDR_HEADER);
524 printf("ID=%04x Rev=%d Len=%03x <?>\n",
531 cap_l1pm(struct device *d, int where)
536 printf("L1 PM Substates\n");
541 if (!config_fetch(d, where + 4, 4))
543 printf("\t\t<unreadable>\n");
547 l1_cap = get_conf_long(d, where + 4);
548 printf("\t\tL1SubCap: ");
549 printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c L1_PM_Substates%c\n",
556 if (BITS(l1_cap, 0, 1) || BITS(l1_cap, 2, 1))
558 printf("\t\t\t PortCommonModeRestoreTime=%dus ",
561 power_on_scale = BITS(l1_cap, 16, 2);
563 printf("PortTPowerOnTime=");
564 switch (power_on_scale)
567 printf("%dus\n", BITS(l1_cap, 19, 5) * 2);
570 printf("%dus\n", BITS(l1_cap, 19, 5) * 10);
573 printf("%dus\n", BITS(l1_cap, 19, 5) * 100);
583 show_ext_caps(struct device *d)
586 char been_there[0x1000];
587 memset(been_there, 0, 0x1000);
593 if (!config_fetch(d, where, 4))
595 header = get_conf_long(d, where);
598 id = header & 0xffff;
599 version = (header >> 16) & 0xf;
600 printf("\tCapabilities: [%03x", where);
602 printf(" v%d", version);
604 if (been_there[where]++)
606 printf("<chain looped>\n");
611 case PCI_EXT_CAP_ID_AER:
614 case PCI_EXT_CAP_ID_DPC:
617 case PCI_EXT_CAP_ID_VC:
618 case PCI_EXT_CAP_ID_VC2:
621 case PCI_EXT_CAP_ID_DSN:
624 case PCI_EXT_CAP_ID_PB:
625 printf("Power Budgeting <?>\n");
627 case PCI_EXT_CAP_ID_RCLINK:
628 cap_rclink(d, where);
630 case PCI_EXT_CAP_ID_RCILINK:
631 printf("Root Complex Internal Link <?>\n");
633 case PCI_EXT_CAP_ID_RCECOLL:
634 printf("Root Complex Event Collector <?>\n");
636 case PCI_EXT_CAP_ID_MFVC:
637 printf("Multi-Function Virtual Channel <?>\n");
639 case PCI_EXT_CAP_ID_RBCB:
640 printf("Root Bridge Control Block <?>\n");
642 case PCI_EXT_CAP_ID_VNDR:
643 cap_evendor(d, where);
645 case PCI_EXT_CAP_ID_ACS:
648 case PCI_EXT_CAP_ID_ARI:
651 case PCI_EXT_CAP_ID_ATS:
654 case PCI_EXT_CAP_ID_SRIOV:
657 case PCI_EXT_CAP_ID_PRI:
660 case PCI_EXT_CAP_ID_TPH:
663 case PCI_EXT_CAP_ID_LTR:
666 case PCI_EXT_CAP_ID_PASID:
669 case PCI_EXT_CAP_ID_L1PM:
673 printf("#%02x\n", id);
676 where = (header >> 20) & ~3;