2 * The PCI Utilities -- Show Extended Capabilities
4 * Copyright (c) 1997--2010 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL.
15 cap_tph(struct device *d, int where)
18 printf("Transaction Processing Hints\n");
22 if (!config_fetch(d, where + PCI_TPH_CAPABILITIES, 4))
25 tph_cap = get_conf_long(d, where + PCI_TPH_CAPABILITIES);
27 if (tph_cap & PCI_TPH_INTVEC_SUP)
28 printf("\t\tInterrupt vector mode supported\n");
29 if (tph_cap & PCI_TPH_DEV_SUP)
30 printf("\t\tDevice specific mode supported\n");
31 if (tph_cap & PCI_TPH_EXT_REQ_SUP)
32 printf("\t\tExtended requester support\n");
34 switch (tph_cap & PCI_TPH_ST_LOC_MASK) {
36 printf("\t\tNo steering table available\n");
39 printf("\t\tSteering table in TPH capability structure\n");
42 printf("\t\tSteering table in MSI-X table\n");
45 printf("\t\tReserved steering table location\n");
51 cap_ltr_scale(u8 scale)
53 return 1 << (scale * 5);
57 cap_ltr(struct device *d, int where)
61 printf("Latency Tolerance Reporting\n");
65 if (!config_fetch(d, where + PCI_LTR_MAX_SNOOP, 4))
68 snoop = get_conf_word(d, where + PCI_LTR_MAX_SNOOP);
69 scale = cap_ltr_scale((snoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK);
70 printf("\t\tMax snoop latency: %lldns\n",
71 ((unsigned long long)snoop & PCI_LTR_VALUE_MASK) * scale);
73 nosnoop = get_conf_word(d, where + PCI_LTR_MAX_NOSNOOP);
74 scale = cap_ltr_scale((nosnoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK);
75 printf("\t\tMax no snoop latency: %lldns\n",
76 ((unsigned long long)nosnoop & PCI_LTR_VALUE_MASK) * scale);
80 cap_dsn(struct device *d, int where)
83 if (!config_fetch(d, where + 4, 8))
85 t1 = get_conf_long(d, where + 4);
86 t2 = get_conf_long(d, where + 8);
87 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
88 t2 >> 24, (t2 >> 16) & 0xff, (t2 >> 8) & 0xff, t2 & 0xff,
89 t1 >> 24, (t1 >> 16) & 0xff, (t1 >> 8) & 0xff, t1 & 0xff);
93 cap_aer(struct device *d, int where)
97 printf("Advanced Error Reporting\n");
101 if (!config_fetch(d, where + PCI_ERR_UNCOR_STATUS, 24))
104 l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS);
105 printf("\t\tUESta:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
106 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
107 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
108 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
109 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
110 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
111 l = get_conf_long(d, where + PCI_ERR_UNCOR_MASK);
112 printf("\t\tUEMsk:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
113 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
114 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
115 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
116 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
117 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
118 l = get_conf_long(d, where + PCI_ERR_UNCOR_SEVER);
119 printf("\t\tUESvrt:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
120 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
121 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
122 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
123 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
124 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
125 l = get_conf_long(d, where + PCI_ERR_COR_STATUS);
126 printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c\n",
127 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
128 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
129 l = get_conf_long(d, where + PCI_ERR_COR_MASK);
130 printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c NonFatalErr%c\n",
131 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
132 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
133 l = get_conf_long(d, where + PCI_ERR_CAP);
134 printf("\t\tAERCap:\tFirst Error Pointer: %02x, GenCap%c CGenEn%c ChkCap%c ChkEn%c\n"
135 "\t\t\tMultHdrRecCap%c MultHdrRecEn%c TLPPfxPres%c HdrLogCap%c\n",
136 PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE),
137 FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE),
138 FLAG(l, PCI_ERR_CAP_MULT_HDRC), FLAG(l, PCI_ERR_CAP_MULT_HDRE),
139 FLAG(l, PCI_ERR_CAP_TLP_PFX), FLAG(l, PCI_ERR_CAP_HDR_LOG));
142 static void cap_dpc(struct device *d, int where)
146 printf("Downstream Port Containment\n");
150 if (!config_fetch(d, where + PCI_DPC_CAP, 8))
153 l = get_conf_word(d, where + PCI_DPC_CAP);
154 printf("\t\tDpcCap:\tINT Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
155 PCI_DPC_CAP_INT_MSG(l), FLAG(l, PCI_DPC_CAP_RP_EXT), FLAG(l, PCI_DPC_CAP_TLP_BLOCK),
156 FLAG(l, PCI_DPC_CAP_SW_TRIGGER), PCI_DPC_CAP_RP_LOG(l), FLAG(l, PCI_DPC_CAP_DL_ACT_ERR));
158 l = get_conf_word(d, where + PCI_DPC_CTL);
159 printf("\t\tDpcCtl:\tTrigger:%x Cmpl%c INT%c ErrCor%c PoisonedTLP%c SwTrigger%c DL_ActiveErr%c\n",
160 PCI_DPC_CTL_TRIGGER(l), FLAG(l, PCI_DPC_CTL_CMPL), FLAG(l, PCI_DPC_CTL_INT),
161 FLAG(l, PCI_DPC_CTL_ERR_COR), FLAG(l, PCI_DPC_CTL_TLP), FLAG(l, PCI_DPC_CTL_SW_TRIGGER),
162 FLAG(l, PCI_DPC_CTL_DL_ACTIVE));
164 l = get_conf_word(d, where + PCI_DPC_STATUS);
165 printf("\t\tDpcSta:\tTrigger%c Reason:%02x INT%c RPBusy%c TriggerExt:%02x RP PIO ErrPtr:%02x\n",
166 FLAG(l, PCI_DPC_STS_TRIGGER), PCI_DPC_STS_REASON(l), FLAG(l, PCI_DPC_STS_INT),
167 FLAG(l, PCI_DPC_STS_RP_BUSY), PCI_DPC_STS_TRIGGER_EXT(l), PCI_DPC_STS_PIO_FEP(l));
169 l = get_conf_word(d, where + PCI_DPC_SOURCE);
170 printf("\t\tSource:\t%04x\n", l);
174 cap_acs(struct device *d, int where)
178 printf("Access Control Services\n");
182 if (!config_fetch(d, where + PCI_ACS_CAP, 4))
185 w = get_conf_word(d, where + PCI_ACS_CAP);
186 printf("\t\tACSCap:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
188 FLAG(w, PCI_ACS_CAP_VALID), FLAG(w, PCI_ACS_CAP_BLOCK), FLAG(w, PCI_ACS_CAP_REQ_RED),
189 FLAG(w, PCI_ACS_CAP_CMPLT_RED), FLAG(w, PCI_ACS_CAP_FORWARD), FLAG(w, PCI_ACS_CAP_EGRESS),
190 FLAG(w, PCI_ACS_CAP_TRANS));
191 w = get_conf_word(d, where + PCI_ACS_CTRL);
192 printf("\t\tACSCtl:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
194 FLAG(w, PCI_ACS_CTRL_VALID), FLAG(w, PCI_ACS_CTRL_BLOCK), FLAG(w, PCI_ACS_CTRL_REQ_RED),
195 FLAG(w, PCI_ACS_CTRL_CMPLT_RED), FLAG(w, PCI_ACS_CTRL_FORWARD), FLAG(w, PCI_ACS_CTRL_EGRESS),
196 FLAG(w, PCI_ACS_CTRL_TRANS));
200 cap_ari(struct device *d, int where)
204 printf("Alternative Routing-ID Interpretation (ARI)\n");
208 if (!config_fetch(d, where + PCI_ARI_CAP, 4))
211 w = get_conf_word(d, where + PCI_ARI_CAP);
212 printf("\t\tARICap:\tMFVC%c ACS%c, Next Function: %d\n",
213 FLAG(w, PCI_ARI_CAP_MFVC), FLAG(w, PCI_ARI_CAP_ACS),
215 w = get_conf_word(d, where + PCI_ARI_CTRL);
216 printf("\t\tARICtl:\tMFVC%c ACS%c, Function Group: %d\n",
217 FLAG(w, PCI_ARI_CTRL_MFVC), FLAG(w, PCI_ARI_CTRL_ACS),
222 cap_ats(struct device *d, int where)
226 printf("Address Translation Service (ATS)\n");
230 if (!config_fetch(d, where + PCI_ATS_CAP, 4))
233 w = get_conf_word(d, where + PCI_ATS_CAP);
234 printf("\t\tATSCap:\tInvalidate Queue Depth: %02x\n", PCI_ATS_CAP_IQD(w));
235 w = get_conf_word(d, where + PCI_ATS_CTRL);
236 printf("\t\tATSCtl:\tEnable%c, Smallest Translation Unit: %02x\n",
237 FLAG(w, PCI_ATS_CTRL_ENABLE), PCI_ATS_CTRL_STU(w));
241 cap_pri(struct device *d, int where)
246 printf("Page Request Interface (PRI)\n");
250 if (!config_fetch(d, where + PCI_PRI_CTRL, 0xc))
253 w = get_conf_word(d, where + PCI_PRI_CTRL);
254 printf("\t\tPRICtl: Enable%c Reset%c\n",
255 FLAG(w, PCI_PRI_CTRL_ENABLE), FLAG(w, PCI_PRI_CTRL_RESET));
256 w = get_conf_word(d, where + PCI_PRI_STATUS);
257 printf("\t\tPRISta: RF%c UPRGI%c Stopped%c\n",
258 FLAG(w, PCI_PRI_STATUS_RF), FLAG(w, PCI_PRI_STATUS_UPRGI),
259 FLAG(w, PCI_PRI_STATUS_STOPPED));
260 l = get_conf_long(d, where + PCI_PRI_MAX_REQ);
261 printf("\t\tPage Request Capacity: %08x, ", l);
262 l = get_conf_long(d, where + PCI_PRI_ALLOC_REQ);
263 printf("Page Request Allocation: %08x\n", l);
267 cap_pasid(struct device *d, int where)
271 printf("Process Address Space ID (PASID)\n");
275 if (!config_fetch(d, where + PCI_PASID_CAP, 4))
278 w = get_conf_word(d, where + PCI_PASID_CAP);
279 printf("\t\tPASIDCap: Exec%c Priv%c, Max PASID Width: %02x\n",
280 FLAG(w, PCI_PASID_CAP_EXEC), FLAG(w, PCI_PASID_CAP_PRIV),
281 PCI_PASID_CAP_WIDTH(w));
282 w = get_conf_word(d, where + PCI_PASID_CTRL);
283 printf("\t\tPASIDCtl: Enable%c Exec%c Priv%c\n",
284 FLAG(w, PCI_PASID_CTRL_ENABLE), FLAG(w, PCI_PASID_CTRL_EXEC),
285 FLAG(w, PCI_PASID_CTRL_PRIV));
289 cap_sriov(struct device *d, int where)
296 printf("Single Root I/O Virtualization (SR-IOV)\n");
300 if (!config_fetch(d, where + PCI_IOV_CAP, 0x3c))
303 l = get_conf_long(d, where + PCI_IOV_CAP);
304 printf("\t\tIOVCap:\tMigration%c, Interrupt Message Number: %03x\n",
305 FLAG(l, PCI_IOV_CAP_VFM), PCI_IOV_CAP_IMN(l));
306 w = get_conf_word(d, where + PCI_IOV_CTRL);
307 printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c\n",
308 FLAG(w, PCI_IOV_CTRL_VFE), FLAG(w, PCI_IOV_CTRL_VFME),
309 FLAG(w, PCI_IOV_CTRL_VFMIE), FLAG(w, PCI_IOV_CTRL_MSE),
310 FLAG(w, PCI_IOV_CTRL_ARI));
311 w = get_conf_word(d, where + PCI_IOV_STATUS);
312 printf("\t\tIOVSta:\tMigration%c\n", FLAG(w, PCI_IOV_STATUS_MS));
313 w = get_conf_word(d, where + PCI_IOV_INITIALVF);
314 printf("\t\tInitial VFs: %d, ", w);
315 w = get_conf_word(d, where + PCI_IOV_TOTALVF);
316 printf("Total VFs: %d, ", w);
317 w = get_conf_word(d, where + PCI_IOV_NUMVF);
318 printf("Number of VFs: %d, ", w);
319 b = get_conf_byte(d, where + PCI_IOV_FDL);
320 printf("Function Dependency Link: %02x\n", b);
321 w = get_conf_word(d, where + PCI_IOV_OFFSET);
322 printf("\t\tVF offset: %d, ", w);
323 w = get_conf_word(d, where + PCI_IOV_STRIDE);
324 printf("stride: %d, ", w);
325 w = get_conf_word(d, where + PCI_IOV_DID);
326 printf("Device ID: %04x\n", w);
327 l = get_conf_long(d, where + PCI_IOV_SUPPS);
328 printf("\t\tSupported Page Size: %08x, ", l);
329 l = get_conf_long(d, where + PCI_IOV_SYSPS);
330 printf("System Page Size: %08x\n", l);
332 for (i=0; i < PCI_IOV_NUM_BAR; i++)
337 l = get_conf_long(d, where + PCI_IOV_BAR_BASE + 4*i);
342 printf("\t\tRegion %d: Memory at ", i);
343 addr = l & PCI_ADDR_MEM_MASK;
344 type = l & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
345 if (type == PCI_BASE_ADDRESS_MEM_TYPE_64)
348 h = get_conf_long(d, where + PCI_IOV_BAR_BASE + (i*4));
351 printf("%08x (%s-bit, %sprefetchable)\n",
353 (type == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32" : "64",
354 (l & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
357 l = get_conf_long(d, where + PCI_IOV_MSAO);
358 printf("\t\tVF Migration: offset: %08x, BIR: %x\n", PCI_IOV_MSA_OFFSET(l),
363 cap_vc(struct device *d, int where)
370 static const char ref_clocks[][6] = { "100ns" };
371 static const char arb_selects[8][7] = { "Fixed", "WRR32", "WRR64", "WRR128", "??4", "??5", "??6", "??7" };
372 static const char vc_arb_selects[8][8] = { "Fixed", "WRR32", "WRR64", "WRR128", "TWRR128", "WRR256", "??6", "??7" };
375 printf("Virtual Channel\n");
379 if (!config_fetch(d, where + 4, 0x1c - 4))
382 cr1 = get_conf_long(d, where + PCI_VC_PORT_REG1);
383 cr2 = get_conf_long(d, where + PCI_VC_PORT_REG2);
384 ctrl = get_conf_word(d, where + PCI_VC_PORT_CTRL);
385 status = get_conf_word(d, where + PCI_VC_PORT_STATUS);
387 evc_cnt = BITS(cr1, 0, 3);
388 printf("\t\tCaps:\tLPEVC=%d RefClk=%s PATEntryBits=%d\n",
390 TABLE(ref_clocks, BITS(cr1, 8, 2), buf),
391 1 << BITS(cr1, 10, 2));
395 if (arb_selects[i][0] != '?' || cr2 & (1 << i))
396 printf("%c%s%c", (i ? ' ' : '\t'), arb_selects[i], FLAG(cr2, 1 << i));
397 arb_table_pos = BITS(cr2, 24, 8);
399 printf("\n\t\tCtrl:\tArbSelect=%s\n", TABLE(arb_selects, BITS(ctrl, 1, 3), buf));
400 printf("\t\tStatus:\tInProgress%c\n", FLAG(status, 1));
404 arb_table_pos = where + 16*arb_table_pos;
405 printf("\t\tPort Arbitration Table [%x] <?>\n", arb_table_pos);
408 for (i=0; i<=evc_cnt; i++)
410 int pos = where + PCI_VC_RES_CAP + 12*i;
415 printf("\t\tVC%d:\t", i);
416 if (!config_fetch(d, pos, 12))
418 printf("<unreadable>\n");
421 rcap = get_conf_long(d, pos);
422 rctrl = get_conf_long(d, pos+4);
423 rstatus = get_conf_word(d, pos+10);
425 pat_pos = BITS(rcap, 24, 8);
426 printf("Caps:\tPATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c\n",
428 BITS(rcap, 16, 6) + 1,
429 FLAG(rcap, 1 << 15));
431 printf("\t\t\tArb:");
433 if (vc_arb_selects[j][0] != '?' || rcap & (1 << j))
434 printf("%c%s%c", (j ? ' ' : '\t'), vc_arb_selects[j], FLAG(rcap, 1 << j));
436 printf("\n\t\t\tCtrl:\tEnable%c ID=%d ArbSelect=%s TC/VC=%02x\n",
437 FLAG(rctrl, 1 << 31),
439 TABLE(vc_arb_selects, BITS(rctrl, 17, 3), buf),
442 printf("\t\t\tStatus:\tNegoPending%c InProgress%c\n",
447 printf("\t\t\tPort Arbitration Table <?>\n");
452 cap_rclink(struct device *d, int where)
457 static const char elt_types[][9] = { "Config", "Egress", "Internal" };
460 printf("Root Complex Link\n");
464 if (!config_fetch(d, where + 4, PCI_RCLINK_LINK1 - 4))
467 esd = get_conf_long(d, where + PCI_RCLINK_ESD);
468 num_links = BITS(esd, 8, 8);
469 printf("\t\tDesc:\tPortNumber=%02x ComponentID=%02x EltType=%s\n",
472 TABLE(elt_types, BITS(esd, 0, 8), buf));
474 for (i=0; i<num_links; i++)
476 int pos = where + PCI_RCLINK_LINK1 + i*PCI_RCLINK_LINK_SIZE;
478 u32 addr_lo, addr_hi;
480 printf("\t\tLink%d:\t", i);
481 if (!config_fetch(d, pos, PCI_RCLINK_LINK_SIZE))
483 printf("<unreadable>\n");
486 desc = get_conf_long(d, pos + PCI_RCLINK_LINK_DESC);
487 addr_lo = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR);
488 addr_hi = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR + 4);
490 printf("Desc:\tTargetPort=%02x TargetComponent=%02x AssocRCRB%c LinkType=%s LinkValid%c\n",
494 ((desc & 2) ? "Config" : "MemMapped"),
502 printf("\t\t\tAddr:\t%02x:%02x.%d CfgSpace=%08x%08x\n",
503 BITS(addr_lo, 20, n),
504 BITS(addr_lo, 15, 5),
505 BITS(addr_lo, 12, 3),
509 printf("\t\t\tAddr:\t%08x%08x\n", addr_hi, addr_lo);
514 cap_evendor(struct device *d, int where)
518 printf("Vendor Specific Information: ");
519 if (!config_fetch(d, where + PCI_EVNDR_HEADER, 4))
521 printf("<unreadable>\n");
525 hdr = get_conf_long(d, where + PCI_EVNDR_HEADER);
526 printf("ID=%04x Rev=%d Len=%03x <?>\n",
532 static int l1pm_calc_pwron(int scale, int value)
547 cap_l1pm(struct device *d, int where)
549 u32 l1_cap, val, scale;
552 printf("L1 PM Substates\n");
557 if (!config_fetch(d, where + PCI_L1PM_SUBSTAT_CAP, 12))
559 printf("\t\t<unreadable>\n");
563 l1_cap = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CAP);
564 printf("\t\tL1SubCap: ");
565 printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c L1_PM_Substates%c\n",
566 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L12),
567 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L11),
568 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L12),
569 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L11),
570 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP));
572 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
574 printf("\t\t\t PortCommonModeRestoreTime=%dus ", BITS(l1_cap, 8, 8));
575 time = l1pm_calc_pwron(BITS(l1_cap, 16, 2), BITS(l1_cap, 19, 5));
577 printf("PortTPowerOnTime=%dus\n", time);
579 printf("PortTPowerOnTime=<error>\n");
582 val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL1);
583 printf("\t\tL1SubCtl1: PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c\n",
584 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L12),
585 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L11),
586 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L12),
587 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L11));
589 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
590 printf("\t\t\t T_CommonMode=%dus", BITS(val, 8, 8));
592 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
594 scale = BITS(val, 29, 3);
596 printf(" LTR1.2_Threshold=<error>");
598 printf(" LTR1.2_Threshold=%lldns", BITS(val, 16, 10) * (unsigned long long) cap_ltr_scale(scale));
602 val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL2);
603 printf("\t\tL1SubCtl2:");
604 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
606 time = l1pm_calc_pwron(BITS(val, 0, 2), BITS(val, 3, 5));
608 printf(" T_PwrOn=%dus", time);
610 printf(" T_PwrOn=<error>");
616 cap_ptm(struct device *d, int where)
621 printf("Precision Time Measurement\n");
626 if (!config_fetch(d, where + 4, 8))
628 printf("\t\t<unreadable>\n");
632 buff = get_conf_long(d, where + 4);
633 printf("\t\tPTMCap: ");
634 printf("Requester:%c Responder:%c Root:%c\n",
639 clock = BITS(buff, 8, 8);
640 printf("\t\tPTMClockGranularity: ");
644 printf("Unimplemented\n");
647 printf("Greater than 254ns\n");
650 printf("%huns\n", clock);
653 buff = get_conf_long(d, where + 8);
654 printf("\t\tPTMControl: ");
655 printf("Enabled:%c RootSelected:%c\n",
659 clock = BITS(buff, 8, 8);
660 printf("\t\tPTMEffectiveGranularity: ");
667 printf("Greater than 254ns\n");
670 printf("%huns\n", clock);
675 show_ext_caps(struct device *d)
678 char been_there[0x1000];
679 memset(been_there, 0, 0x1000);
685 if (!config_fetch(d, where, 4))
687 header = get_conf_long(d, where);
690 id = header & 0xffff;
691 version = (header >> 16) & 0xf;
692 printf("\tCapabilities: [%03x", where);
694 printf(" v%d", version);
696 if (been_there[where]++)
698 printf("<chain looped>\n");
703 case PCI_EXT_CAP_ID_AER:
706 case PCI_EXT_CAP_ID_DPC:
709 case PCI_EXT_CAP_ID_VC:
710 case PCI_EXT_CAP_ID_VC2:
713 case PCI_EXT_CAP_ID_DSN:
716 case PCI_EXT_CAP_ID_PB:
717 printf("Power Budgeting <?>\n");
719 case PCI_EXT_CAP_ID_RCLINK:
720 cap_rclink(d, where);
722 case PCI_EXT_CAP_ID_RCILINK:
723 printf("Root Complex Internal Link <?>\n");
725 case PCI_EXT_CAP_ID_RCECOLL:
726 printf("Root Complex Event Collector <?>\n");
728 case PCI_EXT_CAP_ID_MFVC:
729 printf("Multi-Function Virtual Channel <?>\n");
731 case PCI_EXT_CAP_ID_RBCB:
732 printf("Root Bridge Control Block <?>\n");
734 case PCI_EXT_CAP_ID_VNDR:
735 cap_evendor(d, where);
737 case PCI_EXT_CAP_ID_ACS:
740 case PCI_EXT_CAP_ID_ARI:
743 case PCI_EXT_CAP_ID_ATS:
746 case PCI_EXT_CAP_ID_SRIOV:
749 case PCI_EXT_CAP_ID_PRI:
752 case PCI_EXT_CAP_ID_TPH:
755 case PCI_EXT_CAP_ID_LTR:
758 case PCI_EXT_CAP_ID_PASID:
761 case PCI_EXT_CAP_ID_L1PM:
764 case PCI_EXT_CAP_ID_PTM:
768 printf("#%02x\n", id);
771 where = (header >> 20) & ~3;