2 * The PCI Utilities -- Show Capabilities
4 * Copyright (c) 1997--2010 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL.
15 cap_pm(struct device *d, int where, int cap)
18 static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
20 printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
23 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
24 FLAG(cap, PCI_PM_CAP_PME_CLOCK),
25 FLAG(cap, PCI_PM_CAP_DSI),
26 FLAG(cap, PCI_PM_CAP_D1),
27 FLAG(cap, PCI_PM_CAP_D2),
28 pm_aux_current[(cap & PCI_PM_CAP_AUX_C_MASK) >> 6],
29 FLAG(cap, PCI_PM_CAP_PME_D0),
30 FLAG(cap, PCI_PM_CAP_PME_D1),
31 FLAG(cap, PCI_PM_CAP_PME_D2),
32 FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
33 FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
34 if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
36 t = get_conf_word(d, where + PCI_PM_CTRL);
37 printf("\t\tStatus: D%d NoSoftRst%c PME-Enable%c DSel=%d DScale=%d PME%c\n",
38 t & PCI_PM_CTRL_STATE_MASK,
39 FLAG(t, PCI_PM_CTRL_NO_SOFT_RST),
40 FLAG(t, PCI_PM_CTRL_PME_ENABLE),
41 (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
42 (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
43 FLAG(t, PCI_PM_CTRL_PME_STATUS));
44 b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
46 printf("\t\tBridge: PM%c B3%c\n",
47 FLAG(t, PCI_PM_BPCC_ENABLE),
48 FLAG(~t, PCI_PM_PPB_B2_B3));
52 format_agp_rate(int rate, char *buf, int agp3)
62 c += sprintf(c, "x%d", 1 << (i + 2*agp3));
67 strcpy(buf, "<none>");
71 cap_agp(struct device *d, int where, int cap)
78 ver = (cap >> 4) & 0x0f;
80 printf("AGP version %x.%x\n", ver, rev);
83 if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
85 t = get_conf_long(d, where + PCI_AGP_STATUS);
86 if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
88 format_agp_rate(t & 7, rate, agp3);
89 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
90 ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
91 FLAG(t, PCI_AGP_STATUS_ISOCH),
92 ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
93 ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
94 FLAG(t, PCI_AGP_STATUS_SBA),
95 FLAG(t, PCI_AGP_STATUS_ITA_COH),
96 FLAG(t, PCI_AGP_STATUS_GART64),
97 FLAG(t, PCI_AGP_STATUS_HTRANS),
98 FLAG(t, PCI_AGP_STATUS_64BIT),
99 FLAG(t, PCI_AGP_STATUS_FW),
100 FLAG(t, PCI_AGP_STATUS_AGP3),
102 t = get_conf_long(d, where + PCI_AGP_COMMAND);
103 format_agp_rate(t & 7, rate, agp3);
104 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
105 ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
106 ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
107 ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
108 FLAG(t, PCI_AGP_COMMAND_SBA),
109 FLAG(t, PCI_AGP_COMMAND_AGP),
110 FLAG(t, PCI_AGP_COMMAND_GART64),
111 FLAG(t, PCI_AGP_COMMAND_64BIT),
112 FLAG(t, PCI_AGP_COMMAND_FW),
117 cap_pcix_nobridge(struct device *d, int where)
121 static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
123 printf("PCI-X non-bridge device\n");
128 if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
131 command = get_conf_word(d, where + PCI_PCIX_COMMAND);
132 status = get_conf_long(d, where + PCI_PCIX_STATUS);
133 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
134 FLAG(command, PCI_PCIX_COMMAND_DPERE),
135 FLAG(command, PCI_PCIX_COMMAND_ERO),
136 1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
137 max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
138 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
139 (status & PCI_PCIX_STATUS_BUS) >> 8,
140 (status & PCI_PCIX_STATUS_DEVICE) >> 3,
141 (status & PCI_PCIX_STATUS_FUNCTION),
142 FLAG(status, PCI_PCIX_STATUS_64BIT),
143 FLAG(status, PCI_PCIX_STATUS_133MHZ),
144 FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
145 FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
146 ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
147 1 << (9 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT) >> 21)),
148 max_outstanding[(status & PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS) >> 23],
149 1 << (3 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE) >> 26)),
150 FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
151 FLAG(status, PCI_PCIX_STATUS_266MHZ),
152 FLAG(status, PCI_PCIX_STATUS_533MHZ));
156 cap_pcix_bridge(struct device *d, int where)
158 static const char * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
160 u32 status, upstcr, downstcr;
162 printf("PCI-X bridge device\n");
167 if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
170 secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
171 printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
172 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
173 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
174 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
175 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
176 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
177 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
178 sec_clock_freq[(secstatus & PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ) >> 6]);
179 status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
180 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
181 (status & PCI_PCIX_BRIDGE_STATUS_BUS) >> 8,
182 (status & PCI_PCIX_BRIDGE_STATUS_DEVICE) >> 3,
183 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
184 FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
185 FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
186 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
187 FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
188 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
189 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
190 upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
191 printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
192 (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
193 (upstcr >> 16) & 0xffff);
194 downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
195 printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
196 (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
197 (downstcr >> 16) & 0xffff);
201 cap_pcix(struct device *d, int where)
203 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
205 case PCI_HEADER_TYPE_NORMAL:
206 cap_pcix_nobridge(d, where);
208 case PCI_HEADER_TYPE_BRIDGE:
209 cap_pcix_bridge(d, where);
215 ht_link_width(unsigned width)
217 static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
218 return widths[width];
222 ht_link_freq(unsigned freq)
224 static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
225 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
230 cap_ht_pri(struct device *d, int where, int cmd)
232 u16 lctr0, lcnf0, lctr1, lcnf1, eh;
233 u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
236 printf("HyperTransport: Slave or Primary Interface\n");
240 if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
242 rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
243 if (rid < 0x22 && rid > 0x11)
244 printf("\t\t!!! Possibly incomplete decoding\n");
247 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n";
249 fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n";
251 (cmd & PCI_HT_PRI_CMD_BUID),
252 (cmd & PCI_HT_PRI_CMD_UC) >> 5,
253 FLAG(cmd, PCI_HT_PRI_CMD_MH),
254 FLAG(cmd, PCI_HT_PRI_CMD_DD),
255 FLAG(cmd, PCI_HT_PRI_CMD_DUL));
256 lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
258 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
260 fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
262 FLAG(lctr0, PCI_HT_LCTR_CFLE),
263 FLAG(lctr0, PCI_HT_LCTR_CST),
264 FLAG(lctr0, PCI_HT_LCTR_CFE),
265 FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
266 FLAG(lctr0, PCI_HT_LCTR_INIT),
267 FLAG(lctr0, PCI_HT_LCTR_EOC),
268 FLAG(lctr0, PCI_HT_LCTR_TXO),
269 (lctr0 & PCI_HT_LCTR_CRCERR) >> 8,
270 FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
271 FLAG(lctr0, PCI_HT_LCTR_LSEN),
272 FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
273 FLAG(lctr0, PCI_HT_LCTR_64B));
274 lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
276 fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
278 fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
280 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
281 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
282 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
283 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
284 FLAG(lcnf0, PCI_HT_LCNF_DFI),
285 FLAG(lcnf0, PCI_HT_LCNF_DFO),
286 FLAG(lcnf0, PCI_HT_LCNF_DFIE),
287 FLAG(lcnf0, PCI_HT_LCNF_DFOE));
288 lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
290 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
292 fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
294 FLAG(lctr1, PCI_HT_LCTR_CFLE),
295 FLAG(lctr1, PCI_HT_LCTR_CST),
296 FLAG(lctr1, PCI_HT_LCTR_CFE),
297 FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
298 FLAG(lctr1, PCI_HT_LCTR_INIT),
299 FLAG(lctr1, PCI_HT_LCTR_EOC),
300 FLAG(lctr1, PCI_HT_LCTR_TXO),
301 (lctr1 & PCI_HT_LCTR_CRCERR) >> 8,
302 FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
303 FLAG(lctr1, PCI_HT_LCTR_LSEN),
304 FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
305 FLAG(lctr1, PCI_HT_LCTR_64B));
306 lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
308 fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
310 fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
312 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
313 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
314 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
315 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
316 FLAG(lcnf1, PCI_HT_LCNF_DFI),
317 FLAG(lcnf1, PCI_HT_LCNF_DFO),
318 FLAG(lcnf1, PCI_HT_LCNF_DFIE),
319 FLAG(lcnf1, PCI_HT_LCNF_DFOE));
320 printf("\t\tRevision ID: %u.%02u\n",
321 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
324 lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
325 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
326 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
327 FLAG(lfrer0, PCI_HT_LFRER_PROT),
328 FLAG(lfrer0, PCI_HT_LFRER_OV),
329 FLAG(lfrer0, PCI_HT_LFRER_EOC),
330 FLAG(lfrer0, PCI_HT_LFRER_CTLT));
331 lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
332 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
333 FLAG(lfcap0, PCI_HT_LFCAP_200),
334 FLAG(lfcap0, PCI_HT_LFCAP_300),
335 FLAG(lfcap0, PCI_HT_LFCAP_400),
336 FLAG(lfcap0, PCI_HT_LFCAP_500),
337 FLAG(lfcap0, PCI_HT_LFCAP_600),
338 FLAG(lfcap0, PCI_HT_LFCAP_800),
339 FLAG(lfcap0, PCI_HT_LFCAP_1000),
340 FLAG(lfcap0, PCI_HT_LFCAP_1200),
341 FLAG(lfcap0, PCI_HT_LFCAP_1400),
342 FLAG(lfcap0, PCI_HT_LFCAP_1600),
343 FLAG(lfcap0, PCI_HT_LFCAP_VEND));
344 ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
345 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
346 FLAG(ftr, PCI_HT_FTR_ISOCFC),
347 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
348 FLAG(ftr, PCI_HT_FTR_CRCTM),
349 FLAG(ftr, PCI_HT_FTR_ECTLT),
350 FLAG(ftr, PCI_HT_FTR_64BA),
351 FLAG(ftr, PCI_HT_FTR_UIDRD));
352 lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
353 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
354 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
355 FLAG(lfrer1, PCI_HT_LFRER_PROT),
356 FLAG(lfrer1, PCI_HT_LFRER_OV),
357 FLAG(lfrer1, PCI_HT_LFRER_EOC),
358 FLAG(lfrer1, PCI_HT_LFRER_CTLT));
359 lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
360 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
361 FLAG(lfcap1, PCI_HT_LFCAP_200),
362 FLAG(lfcap1, PCI_HT_LFCAP_300),
363 FLAG(lfcap1, PCI_HT_LFCAP_400),
364 FLAG(lfcap1, PCI_HT_LFCAP_500),
365 FLAG(lfcap1, PCI_HT_LFCAP_600),
366 FLAG(lfcap1, PCI_HT_LFCAP_800),
367 FLAG(lfcap1, PCI_HT_LFCAP_1000),
368 FLAG(lfcap1, PCI_HT_LFCAP_1200),
369 FLAG(lfcap1, PCI_HT_LFCAP_1400),
370 FLAG(lfcap1, PCI_HT_LFCAP_1600),
371 FLAG(lfcap1, PCI_HT_LFCAP_VEND));
372 eh = get_conf_word(d, where + PCI_HT_PRI_EH);
373 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
374 FLAG(eh, PCI_HT_EH_PFLE),
375 FLAG(eh, PCI_HT_EH_OFLE),
376 FLAG(eh, PCI_HT_EH_PFE),
377 FLAG(eh, PCI_HT_EH_OFE),
378 FLAG(eh, PCI_HT_EH_EOCFE),
379 FLAG(eh, PCI_HT_EH_RFE),
380 FLAG(eh, PCI_HT_EH_CRCFE),
381 FLAG(eh, PCI_HT_EH_SERRFE),
382 FLAG(eh, PCI_HT_EH_CF),
383 FLAG(eh, PCI_HT_EH_RE),
384 FLAG(eh, PCI_HT_EH_PNFE),
385 FLAG(eh, PCI_HT_EH_ONFE),
386 FLAG(eh, PCI_HT_EH_EOCNFE),
387 FLAG(eh, PCI_HT_EH_RNFE),
388 FLAG(eh, PCI_HT_EH_CRCNFE),
389 FLAG(eh, PCI_HT_EH_SERRNFE));
390 mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
391 mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
392 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
393 bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
394 printf("\t\tBus Number: %02x\n", bn);
398 cap_ht_sec(struct device *d, int where, int cmd)
400 u16 lctr, lcnf, ftr, eh;
401 u8 rid, lfrer, lfcap, mbu, mlu;
404 printf("HyperTransport: Host or Secondary Interface\n");
408 if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
410 rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
411 if (rid < 0x22 && rid > 0x11)
412 printf("\t\t!!! Possibly incomplete decoding\n");
415 fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
417 fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
419 FLAG(cmd, PCI_HT_SEC_CMD_WR),
420 FLAG(cmd, PCI_HT_SEC_CMD_DE),
421 (cmd & PCI_HT_SEC_CMD_DN) >> 2,
422 FLAG(cmd, PCI_HT_SEC_CMD_CS),
423 FLAG(cmd, PCI_HT_SEC_CMD_HH),
424 FLAG(cmd, PCI_HT_SEC_CMD_AS),
425 FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
426 FLAG(cmd, PCI_HT_SEC_CMD_DUL));
427 lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
429 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
431 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
433 FLAG(lctr, PCI_HT_LCTR_CFLE),
434 FLAG(lctr, PCI_HT_LCTR_CST),
435 FLAG(lctr, PCI_HT_LCTR_CFE),
436 FLAG(lctr, PCI_HT_LCTR_LKFAIL),
437 FLAG(lctr, PCI_HT_LCTR_INIT),
438 FLAG(lctr, PCI_HT_LCTR_EOC),
439 FLAG(lctr, PCI_HT_LCTR_TXO),
440 (lctr & PCI_HT_LCTR_CRCERR) >> 8,
441 FLAG(lctr, PCI_HT_LCTR_ISOCEN),
442 FLAG(lctr, PCI_HT_LCTR_LSEN),
443 FLAG(lctr, PCI_HT_LCTR_EXTCTL),
444 FLAG(lctr, PCI_HT_LCTR_64B));
445 lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
447 fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
449 fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
451 ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
452 ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
453 ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
454 ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
455 FLAG(lcnf, PCI_HT_LCNF_DFI),
456 FLAG(lcnf, PCI_HT_LCNF_DFO),
457 FLAG(lcnf, PCI_HT_LCNF_DFIE),
458 FLAG(lcnf, PCI_HT_LCNF_DFOE));
459 printf("\t\tRevision ID: %u.%02u\n",
460 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
463 lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
464 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
465 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
466 FLAG(lfrer, PCI_HT_LFRER_PROT),
467 FLAG(lfrer, PCI_HT_LFRER_OV),
468 FLAG(lfrer, PCI_HT_LFRER_EOC),
469 FLAG(lfrer, PCI_HT_LFRER_CTLT));
470 lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
471 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
472 FLAG(lfcap, PCI_HT_LFCAP_200),
473 FLAG(lfcap, PCI_HT_LFCAP_300),
474 FLAG(lfcap, PCI_HT_LFCAP_400),
475 FLAG(lfcap, PCI_HT_LFCAP_500),
476 FLAG(lfcap, PCI_HT_LFCAP_600),
477 FLAG(lfcap, PCI_HT_LFCAP_800),
478 FLAG(lfcap, PCI_HT_LFCAP_1000),
479 FLAG(lfcap, PCI_HT_LFCAP_1200),
480 FLAG(lfcap, PCI_HT_LFCAP_1400),
481 FLAG(lfcap, PCI_HT_LFCAP_1600),
482 FLAG(lfcap, PCI_HT_LFCAP_VEND));
483 ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
484 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
485 FLAG(ftr, PCI_HT_FTR_ISOCFC),
486 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
487 FLAG(ftr, PCI_HT_FTR_CRCTM),
488 FLAG(ftr, PCI_HT_FTR_ECTLT),
489 FLAG(ftr, PCI_HT_FTR_64BA),
490 FLAG(ftr, PCI_HT_FTR_UIDRD),
491 FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
492 FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
493 if (ftr & PCI_HT_SEC_FTR_EXTRS)
495 eh = get_conf_word(d, where + PCI_HT_SEC_EH);
496 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
497 FLAG(eh, PCI_HT_EH_PFLE),
498 FLAG(eh, PCI_HT_EH_OFLE),
499 FLAG(eh, PCI_HT_EH_PFE),
500 FLAG(eh, PCI_HT_EH_OFE),
501 FLAG(eh, PCI_HT_EH_EOCFE),
502 FLAG(eh, PCI_HT_EH_RFE),
503 FLAG(eh, PCI_HT_EH_CRCFE),
504 FLAG(eh, PCI_HT_EH_SERRFE),
505 FLAG(eh, PCI_HT_EH_CF),
506 FLAG(eh, PCI_HT_EH_RE),
507 FLAG(eh, PCI_HT_EH_PNFE),
508 FLAG(eh, PCI_HT_EH_ONFE),
509 FLAG(eh, PCI_HT_EH_EOCNFE),
510 FLAG(eh, PCI_HT_EH_RNFE),
511 FLAG(eh, PCI_HT_EH_CRCNFE),
512 FLAG(eh, PCI_HT_EH_SERRNFE));
513 mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
514 mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
515 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
520 cap_ht(struct device *d, int where, int cmd)
524 switch (cmd & PCI_HT_CMD_TYP_HI)
526 case PCI_HT_CMD_TYP_HI_PRI:
527 cap_ht_pri(d, where, cmd);
529 case PCI_HT_CMD_TYP_HI_SEC:
530 cap_ht_sec(d, where, cmd);
534 type = cmd & PCI_HT_CMD_TYP;
537 case PCI_HT_CMD_TYP_SW:
538 printf("HyperTransport: Switch\n");
540 case PCI_HT_CMD_TYP_IDC:
541 printf("HyperTransport: Interrupt Discovery and Configuration\n");
543 case PCI_HT_CMD_TYP_RID:
544 printf("HyperTransport: Revision ID: %u.%02u\n",
545 (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
547 case PCI_HT_CMD_TYP_UIDC:
548 printf("HyperTransport: UnitID Clumping\n");
550 case PCI_HT_CMD_TYP_ECSA:
551 printf("HyperTransport: Extended Configuration Space Access\n");
553 case PCI_HT_CMD_TYP_AM:
554 printf("HyperTransport: Address Mapping\n");
556 case PCI_HT_CMD_TYP_MSIM:
557 printf("HyperTransport: MSI Mapping Enable%c Fixed%c\n",
558 FLAG(cmd, PCI_HT_MSIM_CMD_EN),
559 FLAG(cmd, PCI_HT_MSIM_CMD_FIXD));
560 if (verbose >= 2 && !(cmd & PCI_HT_MSIM_CMD_FIXD))
563 if (!config_fetch(d, where + PCI_HT_MSIM_ADDR_LO, 8))
565 offl = get_conf_long(d, where + PCI_HT_MSIM_ADDR_LO);
566 offh = get_conf_long(d, where + PCI_HT_MSIM_ADDR_HI);
567 printf("\t\tMapping Address Base: %016llx\n", ((unsigned long long)offh << 32) | (offl & ~0xfffff));
570 case PCI_HT_CMD_TYP_DR:
571 printf("HyperTransport: DirectRoute\n");
573 case PCI_HT_CMD_TYP_VCS:
574 printf("HyperTransport: VCSet\n");
576 case PCI_HT_CMD_TYP_RM:
577 printf("HyperTransport: Retry Mode\n");
579 case PCI_HT_CMD_TYP_X86:
580 printf("HyperTransport: X86 (reserved)\n");
583 printf("HyperTransport: #%02x\n", type >> 11);
588 cap_msi(struct device *d, int where, int cap)
594 printf("MSI: Enable%c Count=%d/%d Maskable%c 64bit%c\n",
595 FLAG(cap, PCI_MSI_FLAGS_ENABLE),
596 1 << ((cap & PCI_MSI_FLAGS_QSIZE) >> 4),
597 1 << ((cap & PCI_MSI_FLAGS_QMASK) >> 1),
598 FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
599 FLAG(cap, PCI_MSI_FLAGS_64BIT));
602 is64 = cap & PCI_MSI_FLAGS_64BIT;
603 if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
605 printf("\t\tAddress: ");
608 t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
609 w = get_conf_word(d, where + PCI_MSI_DATA_64);
613 w = get_conf_word(d, where + PCI_MSI_DATA_32);
614 t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
615 printf("%08x Data: %04x\n", t, w);
616 if (cap & PCI_MSI_FLAGS_MASK_BIT)
622 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_64, 8))
624 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_64);
625 pending = get_conf_long(d, where + PCI_MSI_PENDING_64);
629 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_32, 8))
631 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_32);
632 pending = get_conf_long(d, where + PCI_MSI_PENDING_32);
634 printf("\t\tMasking: %08x Pending: %08x\n", mask, pending);
638 static float power_limit(int value, int scale)
640 static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
641 return value * scales[scale];
644 static const char *latency_l0s(int value)
646 static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
647 return latencies[value];
650 static const char *latency_l1(int value)
652 static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
653 return latencies[value];
656 static void cap_express_dev(struct device *d, int where, int type)
661 t = get_conf_long(d, where + PCI_EXP_DEVCAP);
662 printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d",
663 128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
664 (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1);
665 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END))
666 printf(", Latency L0s %s, L1 %s",
667 latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
668 latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
670 printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
671 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
672 (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
673 printf(" AttnBtn%c AttnInd%c PwrInd%c",
674 FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
675 FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
677 FLAG(t, PCI_EXP_DEVCAP_RBE));
678 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END))
680 FLAG(t, PCI_EXP_DEVCAP_FLRESET));
681 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_UPSTREAM) ||
682 (type == PCI_EXP_TYPE_PCI_BRIDGE))
683 printf(" SlotPowerLimit %.3fW",
684 power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
685 (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
688 w = get_conf_word(d, where + PCI_EXP_DEVCTL);
689 printf("\t\tDevCtl:\tReport errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
690 FLAG(w, PCI_EXP_DEVCTL_CERE),
691 FLAG(w, PCI_EXP_DEVCTL_NFERE),
692 FLAG(w, PCI_EXP_DEVCTL_FERE),
693 FLAG(w, PCI_EXP_DEVCTL_URRE));
694 printf("\t\t\tRlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c",
695 FLAG(w, PCI_EXP_DEVCTL_RELAXED),
696 FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
697 FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
698 FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
699 FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
700 if (type == PCI_EXP_TYPE_PCI_BRIDGE)
701 printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE));
702 if (((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END)) &&
703 (t & PCI_EXP_DEVCAP_FLRESET))
704 printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET));
705 printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
706 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
707 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
709 w = get_conf_word(d, where + PCI_EXP_DEVSTA);
710 printf("\t\tDevSta:\tCorrErr%c UncorrErr%c FatalErr%c UnsuppReq%c AuxPwr%c TransPend%c\n",
711 FLAG(w, PCI_EXP_DEVSTA_CED),
712 FLAG(w, PCI_EXP_DEVSTA_NFED),
713 FLAG(w, PCI_EXP_DEVSTA_FED),
714 FLAG(w, PCI_EXP_DEVSTA_URD),
715 FLAG(w, PCI_EXP_DEVSTA_AUXPD),
716 FLAG(w, PCI_EXP_DEVSTA_TRPND));
719 static char *link_speed(int speed)
736 static char *aspm_support(int code)
741 return "not supported";
753 static const char *aspm_enabled(int code)
755 static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
759 static void cap_express_link(struct device *d, int where, int type)
764 t = get_conf_long(d, where + PCI_EXP_LNKCAP);
765 aspm = (t & PCI_EXP_LNKCAP_ASPM) >> 10;
766 printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s",
768 link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
772 printf(", Exit Latency ");
774 printf("L0s %s", latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12));
776 printf("%sL1 %s", (aspm & 1) ? ", " : "",
777 latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
780 printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c ASPMOptComp%c\n",
781 FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
782 FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
783 FLAG(t, PCI_EXP_LNKCAP_DLLA),
784 FLAG(t, PCI_EXP_LNKCAP_LBNC),
785 FLAG(t, PCI_EXP_LNKCAP_AOC));
787 w = get_conf_word(d, where + PCI_EXP_LNKCTL);
788 printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
789 if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
790 (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
791 printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
792 printf(" Disabled%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
793 FLAG(w, PCI_EXP_LNKCTL_DISABLE),
794 FLAG(w, PCI_EXP_LNKCTL_CLOCK),
795 FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
796 FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
797 FLAG(w, PCI_EXP_LNKCTL_HWAUTWD),
798 FLAG(w, PCI_EXP_LNKCTL_BWMIE),
799 FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
801 w = get_conf_word(d, where + PCI_EXP_LNKSTA);
802 printf("\t\tLnkSta:\tSpeed %s, Width x%d, TrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
803 link_speed(w & PCI_EXP_LNKSTA_SPEED),
804 (w & PCI_EXP_LNKSTA_WIDTH) >> 4,
805 FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
806 FLAG(w, PCI_EXP_LNKSTA_TRAIN),
807 FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
808 FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
809 FLAG(w, PCI_EXP_LNKSTA_BWMGMT),
810 FLAG(w, PCI_EXP_LNKSTA_AUTBW));
813 static const char *indicator(int code)
815 static const char *names[] = { "Unknown", "On", "Blink", "Off" };
819 static void cap_express_slot(struct device *d, int where)
824 t = get_conf_long(d, where + PCI_EXP_SLTCAP);
825 printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c\n",
826 FLAG(t, PCI_EXP_SLTCAP_ATNB),
827 FLAG(t, PCI_EXP_SLTCAP_PWRC),
828 FLAG(t, PCI_EXP_SLTCAP_MRL),
829 FLAG(t, PCI_EXP_SLTCAP_ATNI),
830 FLAG(t, PCI_EXP_SLTCAP_PWRI),
831 FLAG(t, PCI_EXP_SLTCAP_HPC),
832 FLAG(t, PCI_EXP_SLTCAP_HPS));
833 printf("\t\t\tSlot #%d, PowerLimit %.3fW; Interlock%c NoCompl%c\n",
834 (t & PCI_EXP_SLTCAP_PSN) >> 19,
835 power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15),
836 FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
837 FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP));
839 w = get_conf_word(d, where + PCI_EXP_SLTCTL);
840 printf("\t\tSltCtl:\tEnable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c\n",
841 FLAG(w, PCI_EXP_SLTCTL_ATNB),
842 FLAG(w, PCI_EXP_SLTCTL_PWRF),
843 FLAG(w, PCI_EXP_SLTCTL_MRLS),
844 FLAG(w, PCI_EXP_SLTCTL_PRSD),
845 FLAG(w, PCI_EXP_SLTCTL_CMDC),
846 FLAG(w, PCI_EXP_SLTCTL_HPIE),
847 FLAG(w, PCI_EXP_SLTCTL_LLCHG));
848 printf("\t\t\tControl: AttnInd %s, PwrInd %s, Power%c Interlock%c\n",
849 indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
850 indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
851 FLAG(w, PCI_EXP_SLTCTL_PWRC),
852 FLAG(w, PCI_EXP_SLTCTL_INTERLOCK));
854 w = get_conf_word(d, where + PCI_EXP_SLTSTA);
855 printf("\t\tSltSta:\tStatus: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c\n",
856 FLAG(w, PCI_EXP_SLTSTA_ATNB),
857 FLAG(w, PCI_EXP_SLTSTA_PWRF),
858 FLAG(w, PCI_EXP_SLTSTA_MRL_ST),
859 FLAG(w, PCI_EXP_SLTSTA_CMDC),
860 FLAG(w, PCI_EXP_SLTSTA_PRES),
861 FLAG(w, PCI_EXP_SLTSTA_INTERLOCK));
862 printf("\t\t\tChanged: MRL%c PresDet%c LinkState%c\n",
863 FLAG(w, PCI_EXP_SLTSTA_MRLS),
864 FLAG(w, PCI_EXP_SLTSTA_PRSD),
865 FLAG(w, PCI_EXP_SLTSTA_LLCHG));
868 static void cap_express_root(struct device *d, int where)
870 u32 w = get_conf_word(d, where + PCI_EXP_RTCTL);
871 printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n",
872 FLAG(w, PCI_EXP_RTCTL_SECEE),
873 FLAG(w, PCI_EXP_RTCTL_SENFEE),
874 FLAG(w, PCI_EXP_RTCTL_SEFEE),
875 FLAG(w, PCI_EXP_RTCTL_PMEIE),
876 FLAG(w, PCI_EXP_RTCTL_CRSVIS));
878 w = get_conf_word(d, where + PCI_EXP_RTCAP);
879 printf("\t\tRootCap: CRSVisible%c\n",
880 FLAG(w, PCI_EXP_RTCAP_CRSVIS));
882 w = get_conf_long(d, where + PCI_EXP_RTSTA);
883 printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
884 w & PCI_EXP_RTSTA_PME_REQID,
885 FLAG(w, PCI_EXP_RTSTA_PME_STATUS),
886 FLAG(w, PCI_EXP_RTSTA_PME_PENDING));
889 static const char *cap_express_dev2_timeout_range(int type)
891 /* Decode Completion Timeout Ranges. */
895 return "Not Supported";
915 static const char *cap_express_dev2_timeout_value(int type)
917 /* Decode Completion Timeout Value. */
921 return "50us to 50ms";
923 return "50us to 100us";
925 return "1ms to 10ms";
927 return "16ms to 55ms";
929 return "65ms to 210ms";
931 return "260ms to 900ms";
943 static const char *cap_express_devcap2_obff(int obff)
948 return "Via message";
952 return "Via message/WAKE#";
954 return "Not Supported";
958 static const char *cap_express_devctl2_obff(int obff)
965 return "Via message A";
967 return "Via message B";
976 device_has_memory_space_bar(struct device *d)
978 struct pci_dev *p = d->dev;
982 if (p->base_addr[i] && p->size[i])
984 if (!(p->base_addr[i] & PCI_BASE_ADDRESS_SPACE_IO))
993 static void cap_express_dev2(struct device *d, int where, int type)
997 int has_mem_bar = device_has_memory_space_bar(d);
999 l = get_conf_long(d, where + PCI_EXP_DEVCAP2);
1000 printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c, LTR%c, OBFF %s",
1001 cap_express_dev2_timeout_range(PCI_EXP_DEV2_TIMEOUT_RANGE(l)),
1002 FLAG(l, PCI_EXP_DEV2_TIMEOUT_DIS),
1003 FLAG(l, PCI_EXP_DEVCAP2_LTR),
1004 cap_express_devcap2_obff(PCI_EXP_DEVCAP2_OBFF(l)));
1005 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
1006 printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEV2_ARI));
1009 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1010 type == PCI_EXP_TYPE_DOWNSTREAM || has_mem_bar)
1012 printf("\t\t\t AtomicOpsCap:");
1013 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1014 type == PCI_EXP_TYPE_DOWNSTREAM)
1015 printf(" Routing%c", FLAG(l, PCI_EXP_DEVCAP2_ATOMICOP_ROUTING));
1016 if (type == PCI_EXP_TYPE_ROOT_PORT || has_mem_bar)
1017 printf(" 32bit%c 64bit%c 128bitCAS%c",
1018 FLAG(l, PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP),
1019 FLAG(l, PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP),
1020 FLAG(l, PCI_EXP_DEVCAP2_128BIT_CAS_COMP));
1024 w = get_conf_word(d, where + PCI_EXP_DEVCTL2);
1025 printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c, LTR%c, OBFF %s",
1026 cap_express_dev2_timeout_value(PCI_EXP_DEV2_TIMEOUT_VALUE(w)),
1027 FLAG(w, PCI_EXP_DEV2_TIMEOUT_DIS),
1028 FLAG(w, PCI_EXP_DEV2_LTR),
1029 cap_express_devctl2_obff(PCI_EXP_DEV2_OBFF(w)));
1030 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
1031 printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEV2_ARI));
1034 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1035 type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ENDPOINT ||
1036 type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
1038 printf("\t\t\t AtomicOpsCtl:");
1039 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT ||
1040 type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
1041 printf(" ReqEn%c", FLAG(w, PCI_EXP_DEV2_ATOMICOP_REQUESTER_EN));
1042 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1043 type == PCI_EXP_TYPE_DOWNSTREAM)
1044 printf(" EgressBlck%c", FLAG(w, PCI_EXP_DEV2_ATOMICOP_EGRESS_BLOCK));
1049 static const char *cap_express_link2_speed(int type)
1053 case 0: /* hardwire to 0 means only the 2.5GT/s is supported */
1067 static const char *cap_express_link2_deemphasis(int type)
1080 static const char *cap_express_link2_transmargin(int type)
1085 return "Normal Operating Range";
1087 return "800-1200mV(full-swing)/400-700mV(half-swing)";
1092 return "200-400mV(full-swing)/100-200mV(half-swing)";
1098 static void cap_express_link2(struct device *d, int where, int type)
1102 if (!((type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_LEG_END) &&
1103 (d->dev->dev != 0 || d->dev->func != 0))) {
1104 w = get_conf_word(d, where + PCI_EXP_LNKCTL2);
1105 printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c",
1106 cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w)),
1107 FLAG(w, PCI_EXP_LNKCTL2_CMPLNC),
1108 FLAG(w, PCI_EXP_LNKCTL2_SPEED_DIS));
1109 if (type == PCI_EXP_TYPE_DOWNSTREAM)
1110 printf(", Selectable De-emphasis: %s",
1111 cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w)));
1113 "\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n"
1114 "\t\t\t Compliance De-emphasis: %s\n",
1115 cap_express_link2_transmargin(PCI_EXP_LNKCTL2_MARGIN(w)),
1116 FLAG(w, PCI_EXP_LNKCTL2_MOD_CMPLNC),
1117 FLAG(w, PCI_EXP_LNKCTL2_CMPLNC_SOS),
1118 cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_COM_DEEMPHASIS(w)));
1121 w = get_conf_word(d, where + PCI_EXP_LNKSTA2);
1122 printf("\t\tLnkSta2: Current De-emphasis Level: %s, EqualizationComplete%c, EqualizationPhase1%c\n"
1123 "\t\t\t EqualizationPhase2%c, EqualizationPhase3%c, LinkEqualizationRequest%c\n",
1124 cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)),
1125 FLAG(w, PCI_EXP_LINKSTA2_EQU_COMP),
1126 FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE1),
1127 FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE2),
1128 FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE3),
1129 FLAG(w, PCI_EXP_LINKSTA2_EQU_REQ));
1132 static void cap_express_slot2(struct device *d UNUSED, int where UNUSED)
1134 /* No capabilities that require this field in PCIe rev2.0 spec. */
1138 cap_express(struct device *d, int where, int cap)
1140 int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1147 printf("(v%d) ", cap & PCI_EXP_FLAGS_VERS);
1150 case PCI_EXP_TYPE_ENDPOINT:
1153 case PCI_EXP_TYPE_LEG_END:
1154 printf("Legacy Endpoint");
1156 case PCI_EXP_TYPE_ROOT_PORT:
1157 slot = cap & PCI_EXP_FLAGS_SLOT;
1158 printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1160 case PCI_EXP_TYPE_UPSTREAM:
1161 printf("Upstream Port");
1163 case PCI_EXP_TYPE_DOWNSTREAM:
1164 slot = cap & PCI_EXP_FLAGS_SLOT;
1165 printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1167 case PCI_EXP_TYPE_PCI_BRIDGE:
1168 printf("PCI-Express to PCI/PCI-X Bridge");
1170 case PCI_EXP_TYPE_PCIE_BRIDGE:
1171 slot = cap & PCI_EXP_FLAGS_SLOT;
1172 printf("PCI/PCI-X to PCI-Express Bridge (Slot%c)",
1173 FLAG(cap, PCI_EXP_FLAGS_SLOT));
1175 case PCI_EXP_TYPE_ROOT_INT_EP:
1177 printf("Root Complex Integrated Endpoint");
1179 case PCI_EXP_TYPE_ROOT_EC:
1181 printf("Root Complex Event Collector");
1184 printf("Unknown type %d", type);
1186 printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1193 if (type == PCI_EXP_TYPE_ROOT_PORT)
1195 if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1198 cap_express_dev(d, where, type);
1200 cap_express_link(d, where, type);
1202 cap_express_slot(d, where);
1203 if (type == PCI_EXP_TYPE_ROOT_PORT)
1204 cap_express_root(d, where);
1206 if ((cap & PCI_EXP_FLAGS_VERS) < 2)
1212 if (!config_fetch(d, where + PCI_EXP_DEVCAP2, size))
1215 cap_express_dev2(d, where, type);
1217 cap_express_link2(d, where, type);
1219 cap_express_slot2(d, where);
1224 cap_msix(struct device *d, int where, int cap)
1228 printf("MSI-X: Enable%c Count=%d Masked%c\n",
1229 FLAG(cap, PCI_MSIX_ENABLE),
1230 (cap & PCI_MSIX_TABSIZE) + 1,
1231 FLAG(cap, PCI_MSIX_MASK));
1232 if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1235 off = get_conf_long(d, where + PCI_MSIX_TABLE);
1236 printf("\t\tVector table: BAR=%d offset=%08x\n",
1237 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1238 off = get_conf_long(d, where + PCI_MSIX_PBA);
1239 printf("\t\tPBA: BAR=%d offset=%08x\n",
1240 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1246 int esr = cap & 0xff;
1249 printf("Slot ID: %d slots, First%c, chassis %02x\n",
1250 esr & PCI_SID_ESR_NSLOTS,
1251 FLAG(esr, PCI_SID_ESR_FIC),
1256 cap_ssvid(struct device *d, int where)
1258 u16 subsys_v, subsys_d;
1259 char ssnamebuf[256];
1261 if (!config_fetch(d, where, 8))
1263 subsys_v = get_conf_word(d, where + PCI_SSVID_VENDOR);
1264 subsys_d = get_conf_word(d, where + PCI_SSVID_DEVICE);
1265 printf("Subsystem: %s\n",
1266 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1267 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1268 d->dev->vendor_id, d->dev->device_id, subsys_v, subsys_d));
1272 cap_debug_port(int cap)
1274 int bar = cap >> 13;
1275 int pos = cap & 0x1fff;
1276 printf("Debug port: BAR=%d offset=%04x\n", bar, pos);
1280 cap_af(struct device *d, int where)
1284 printf("PCI Advanced Features\n");
1285 if (verbose < 2 || !config_fetch(d, where + PCI_AF_CAP, 3))
1288 reg = get_conf_byte(d, where + PCI_AF_CAP);
1289 printf("\t\tAFCap: TP%c FLR%c\n", FLAG(reg, PCI_AF_CAP_TP),
1290 FLAG(reg, PCI_AF_CAP_FLR));
1291 reg = get_conf_byte(d, where + PCI_AF_CTRL);
1292 printf("\t\tAFCtrl: FLR%c\n", FLAG(reg, PCI_AF_CTRL_FLR));
1293 reg = get_conf_byte(d, where + PCI_AF_STATUS);
1294 printf("\t\tAFStatus: TP%c\n", FLAG(reg, PCI_AF_STATUS_TP));
1298 cap_sata_hba(struct device *d, int where, int cap)
1303 printf("SATA HBA v%d.%d", BITS(cap, 4, 4), BITS(cap, 0, 4));
1304 if (verbose < 2 || !config_fetch(d, where + PCI_SATA_HBA_BARS, 4))
1310 bars = get_conf_long(d, where + PCI_SATA_HBA_BARS);
1311 bar = BITS(bars, 0, 4);
1312 if (bar >= 4 && bar <= 9)
1313 printf(" BAR%d Offset=%08x\n", bar - 4, BITS(bars, 4, 20));
1315 printf(" InCfgSpace\n");
1317 printf(" BAR??%d\n", bar);
1320 static const char *cap_ea_property(int p, int is_secondary)
1324 return "memory space, non-prefetchable";
1326 return "memory space, prefetchable";
1330 return "VF memory space, prefetchable";
1332 return "VF memory space, non-prefetchable";
1334 return "allocation behind bridge, non-prefetchable memory";
1336 return "allocation behind bridge, prefetchable memory";
1338 return "allocation behind bridge, I/O space";
1340 return "memory space resource unavailable for use";
1342 return "I/O space resource unavailable for use";
1345 return "entry unavailable for use, PrimaryProperties should be used";
1347 return "entry unavailable for use";
1353 static void cap_ea(struct device *d, int where, int cap)
1356 int entry_base = where + 4;
1357 int num_entries = BITS(cap, 0, 6);
1358 u8 htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1360 printf("Enhanced Allocation (EA): NumEntries=%u", num_entries);
1361 if (htype == PCI_HEADER_TYPE_BRIDGE) {
1362 byte fixed_sub, fixed_sec;
1365 if (!config_fetch(d, where + 4, 2)) {
1369 fixed_sec = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SECONDARY);
1370 fixed_sub = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SUBORDINATE);
1371 printf(", secondary=%d, subordinate=%d", fixed_sec, fixed_sub);
1377 for (entry = 0; entry < num_entries; entry++) {
1378 int max_offset_high_pos, has_base_high, has_max_offset_high;
1380 u32 base, max_offset;
1381 int es, bei, pp, sp;
1382 const char *prop_text;
1384 if (!config_fetch(d, entry_base, 4))
1386 entry_header = get_conf_long(d, entry_base);
1387 es = BITS(entry_header, 0, 3);
1388 bei = BITS(entry_header, 4, 4);
1389 pp = BITS(entry_header, 8, 8);
1390 sp = BITS(entry_header, 16, 8);
1391 if (!config_fetch(d, entry_base + 4, es * 4))
1393 printf("\t\tEntry %u: Enable%c Writable%c EntrySize=%u\n", entry,
1394 FLAG(entry_header, PCI_EA_CAP_ENT_ENABLE),
1395 FLAG(entry_header, PCI_EA_CAP_ENT_WRITABLE), es);
1396 printf("\t\t\t BAR Equivalent Indicator: ");
1404 printf("BAR %u", bei);
1407 printf("resource behind function");
1410 printf("not indicated");
1413 printf("expansion ROM");
1421 printf("VF-BAR %u", bei - 9);
1429 prop_text = cap_ea_property(pp, 0);
1430 printf("\t\t\t PrimaryProperties: ");
1432 printf("%s\n", prop_text);
1434 printf("[%02x]\n", pp);
1436 prop_text = cap_ea_property(sp, 1);
1437 printf("\t\t\t SecondaryProperties: ");
1439 printf("%s\n", prop_text);
1441 printf("[%02x]\n", sp);
1443 base = get_conf_long(d, entry_base + 4);
1444 has_base_high = ((base & 2) != 0);
1447 max_offset = get_conf_long(d, entry_base + 8);
1448 has_max_offset_high = ((max_offset & 2) != 0);
1450 max_offset_high_pos = entry_base + 12;
1452 printf("\t\t\t Base: ");
1453 if (has_base_high) {
1454 u32 base_high = get_conf_long(d, entry_base + 12);
1456 printf("%x", base_high);
1457 max_offset_high_pos += 4;
1459 printf("%08x\n", base);
1461 printf("\t\t\t MaxOffset: ");
1462 if (has_max_offset_high) {
1463 u32 max_offset_high = get_conf_long(d, max_offset_high_pos);
1465 printf("%x", max_offset_high);
1467 printf("%08x\n", max_offset);
1469 entry_base += 4 + 4 * es;
1474 show_caps(struct device *d, int where)
1476 int can_have_ext_caps = 0;
1479 if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1481 byte been_there[256];
1482 where = get_conf_byte(d, where) & ~3;
1483 memset(been_there, 0, 256);
1487 printf("\tCapabilities: ");
1488 if (!config_fetch(d, where, 4))
1490 puts("<access denied>");
1493 id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1494 next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1495 cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1496 printf("[%02x] ", where);
1497 if (been_there[where]++)
1499 printf("<chain looped>\n");
1504 printf("<chain broken>\n");
1510 cap_pm(d, where, cap);
1512 case PCI_CAP_ID_AGP:
1513 cap_agp(d, where, cap);
1515 case PCI_CAP_ID_VPD:
1518 case PCI_CAP_ID_SLOTID:
1521 case PCI_CAP_ID_MSI:
1522 cap_msi(d, where, cap);
1524 case PCI_CAP_ID_CHSWP:
1525 printf("CompactPCI hot-swap <?>\n");
1527 case PCI_CAP_ID_PCIX:
1529 can_have_ext_caps = 1;
1532 cap_ht(d, where, cap);
1534 case PCI_CAP_ID_VNDR:
1535 show_vendor_caps(d, where, cap);
1537 case PCI_CAP_ID_DBG:
1538 cap_debug_port(cap);
1540 case PCI_CAP_ID_CCRC:
1541 printf("CompactPCI central resource control <?>\n");
1543 case PCI_CAP_ID_HOTPLUG:
1544 printf("Hot-plug capable\n");
1546 case PCI_CAP_ID_SSVID:
1547 cap_ssvid(d, where);
1549 case PCI_CAP_ID_AGP3:
1550 printf("AGP3 <?>\n");
1552 case PCI_CAP_ID_SECURE:
1553 printf("Secure device <?>\n");
1555 case PCI_CAP_ID_EXP:
1556 type = cap_express(d, where, cap);
1557 can_have_ext_caps = 1;
1559 case PCI_CAP_ID_MSIX:
1560 cap_msix(d, where, cap);
1562 case PCI_CAP_ID_SATA:
1563 cap_sata_hba(d, where, cap);
1569 cap_ea(d, where, cap);
1572 printf("#%02x [%04x]\n", id, cap);
1577 if (can_have_ext_caps)
1578 show_ext_caps(d, type);