2 * The PCI Utilities -- Show Capabilities
4 * Copyright (c) 1997--2018 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL v2+.
8 * SPDX-License-Identifier: GPL-2.0-or-later
17 cap_pm(struct device *d, int where, int cap)
20 static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
22 printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
25 printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
26 FLAG(cap, PCI_PM_CAP_PME_CLOCK),
27 FLAG(cap, PCI_PM_CAP_DSI),
28 FLAG(cap, PCI_PM_CAP_D1),
29 FLAG(cap, PCI_PM_CAP_D2),
30 pm_aux_current[(cap & PCI_PM_CAP_AUX_C_MASK) >> 6],
31 FLAG(cap, PCI_PM_CAP_PME_D0),
32 FLAG(cap, PCI_PM_CAP_PME_D1),
33 FLAG(cap, PCI_PM_CAP_PME_D2),
34 FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
35 FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
36 if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
38 t = get_conf_word(d, where + PCI_PM_CTRL);
39 printf("\t\tStatus: D%d NoSoftRst%c PME-Enable%c DSel=%d DScale=%d PME%c\n",
40 t & PCI_PM_CTRL_STATE_MASK,
41 FLAG(t, PCI_PM_CTRL_NO_SOFT_RST),
42 FLAG(t, PCI_PM_CTRL_PME_ENABLE),
43 (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
44 (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
45 FLAG(t, PCI_PM_CTRL_PME_STATUS));
46 b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
48 printf("\t\tBridge: PM%c B3%c\n",
49 FLAG(b, PCI_PM_BPCC_ENABLE),
50 FLAG(~b, PCI_PM_PPB_B2_B3));
54 format_agp_rate(int rate, char *buf, int agp3)
64 c += sprintf(c, "x%d", 1 << (i + 2*agp3));
69 strcpy(buf, "<none>");
73 cap_agp(struct device *d, int where, int cap)
80 ver = (cap >> 4) & 0x0f;
82 printf("AGP version %x.%x\n", ver, rev);
85 if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
87 t = get_conf_long(d, where + PCI_AGP_STATUS);
88 if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
90 format_agp_rate(t & 7, rate, agp3);
91 printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
92 ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
93 FLAG(t, PCI_AGP_STATUS_ISOCH),
94 ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
95 ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
96 FLAG(t, PCI_AGP_STATUS_SBA),
97 FLAG(t, PCI_AGP_STATUS_ITA_COH),
98 FLAG(t, PCI_AGP_STATUS_GART64),
99 FLAG(t, PCI_AGP_STATUS_HTRANS),
100 FLAG(t, PCI_AGP_STATUS_64BIT),
101 FLAG(t, PCI_AGP_STATUS_FW),
102 FLAG(t, PCI_AGP_STATUS_AGP3),
104 t = get_conf_long(d, where + PCI_AGP_COMMAND);
105 format_agp_rate(t & 7, rate, agp3);
106 printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
107 ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
108 ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
109 ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
110 FLAG(t, PCI_AGP_COMMAND_SBA),
111 FLAG(t, PCI_AGP_COMMAND_AGP),
112 FLAG(t, PCI_AGP_COMMAND_GART64),
113 FLAG(t, PCI_AGP_COMMAND_64BIT),
114 FLAG(t, PCI_AGP_COMMAND_FW),
119 cap_pcix_nobridge(struct device *d, int where)
123 static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
125 printf("PCI-X non-bridge device\n");
130 if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
133 command = get_conf_word(d, where + PCI_PCIX_COMMAND);
134 status = get_conf_long(d, where + PCI_PCIX_STATUS);
135 printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
136 FLAG(command, PCI_PCIX_COMMAND_DPERE),
137 FLAG(command, PCI_PCIX_COMMAND_ERO),
138 1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
139 max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
140 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
141 (status & PCI_PCIX_STATUS_BUS) >> 8,
142 (status & PCI_PCIX_STATUS_DEVICE) >> 3,
143 (status & PCI_PCIX_STATUS_FUNCTION),
144 FLAG(status, PCI_PCIX_STATUS_64BIT),
145 FLAG(status, PCI_PCIX_STATUS_133MHZ),
146 FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
147 FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
148 ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
149 1 << (9 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT) >> 21)),
150 max_outstanding[(status & PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS) >> 23],
151 1 << (3 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE) >> 26)),
152 FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
153 FLAG(status, PCI_PCIX_STATUS_266MHZ),
154 FLAG(status, PCI_PCIX_STATUS_533MHZ));
158 cap_pcix_bridge(struct device *d, int where)
160 static const char * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
162 u32 status, upstcr, downstcr;
164 printf("PCI-X bridge device\n");
169 if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
172 secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
173 printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
174 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
175 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
176 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
177 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
178 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
179 FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
180 sec_clock_freq[(secstatus & PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ) >> 6]);
181 status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
182 printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
183 (status & PCI_PCIX_BRIDGE_STATUS_BUS) >> 8,
184 (status & PCI_PCIX_BRIDGE_STATUS_DEVICE) >> 3,
185 (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
186 FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
187 FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
188 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
189 FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
190 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
191 FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
192 upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
193 printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
194 (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
195 (upstcr >> 16) & 0xffff);
196 downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
197 printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
198 (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
199 (downstcr >> 16) & 0xffff);
203 cap_pcix(struct device *d, int where)
205 switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
207 case PCI_HEADER_TYPE_NORMAL:
208 cap_pcix_nobridge(d, where);
210 case PCI_HEADER_TYPE_BRIDGE:
211 cap_pcix_bridge(d, where);
217 ht_link_width(unsigned width)
219 static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
220 return widths[width];
224 ht_link_freq(unsigned freq)
226 static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
227 "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
232 cap_ht_pri(struct device *d, int where, int cmd)
234 u16 lctr0, lcnf0, lctr1, lcnf1, eh;
235 u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
237 printf("HyperTransport: Slave or Primary Interface\n");
241 if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
243 rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
244 if (rid < 0x22 && rid > 0x11)
245 printf("\t\t!!! Possibly incomplete decoding\n");
247 printf("\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c",
248 (cmd & PCI_HT_PRI_CMD_BUID),
249 (cmd & PCI_HT_PRI_CMD_UC) >> 5,
250 FLAG(cmd, PCI_HT_PRI_CMD_MH),
251 FLAG(cmd, PCI_HT_PRI_CMD_DD));
253 printf(" DUL%c", FLAG(cmd, PCI_HT_PRI_CMD_DUL));
256 lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
257 printf("\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x",
258 FLAG(lctr0, PCI_HT_LCTR_CFLE),
259 FLAG(lctr0, PCI_HT_LCTR_CST),
260 FLAG(lctr0, PCI_HT_LCTR_CFE),
261 FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
262 FLAG(lctr0, PCI_HT_LCTR_INIT),
263 FLAG(lctr0, PCI_HT_LCTR_EOC),
264 FLAG(lctr0, PCI_HT_LCTR_TXO),
265 (lctr0 & PCI_HT_LCTR_CRCERR) >> 8);
267 printf(" IsocEn%c LSEn%c ExtCTL%c 64b%c",
268 FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
269 FLAG(lctr0, PCI_HT_LCTR_LSEN),
270 FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
271 FLAG(lctr0, PCI_HT_LCTR_64B));
274 lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
276 printf("\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n",
277 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
278 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
279 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
280 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12));
282 printf("\t\tLink Config 0: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
283 ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
284 FLAG(lcnf0, PCI_HT_LCNF_DFI),
285 ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
286 FLAG(lcnf0, PCI_HT_LCNF_DFO),
287 ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
288 FLAG(lcnf0, PCI_HT_LCNF_DFIE),
289 ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
290 FLAG(lcnf0, PCI_HT_LCNF_DFOE));
292 lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
293 printf("\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x",
294 FLAG(lctr1, PCI_HT_LCTR_CFLE),
295 FLAG(lctr1, PCI_HT_LCTR_CST),
296 FLAG(lctr1, PCI_HT_LCTR_CFE),
297 FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
298 FLAG(lctr1, PCI_HT_LCTR_INIT),
299 FLAG(lctr1, PCI_HT_LCTR_EOC),
300 FLAG(lctr1, PCI_HT_LCTR_TXO),
301 (lctr1 & PCI_HT_LCTR_CRCERR) >> 8);
303 printf(" IsocEn%c LSEn%c ExtCTL%c 64b%c",
304 FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
305 FLAG(lctr1, PCI_HT_LCTR_LSEN),
306 FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
307 FLAG(lctr1, PCI_HT_LCTR_64B));
310 lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
312 printf("\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n",
313 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
314 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
315 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
316 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12));
318 printf("\t\tLink Config 1: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
319 ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
320 FLAG(lcnf1, PCI_HT_LCNF_DFI),
321 ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
322 FLAG(lcnf1, PCI_HT_LCNF_DFO),
323 ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
324 FLAG(lcnf1, PCI_HT_LCNF_DFIE),
325 ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
326 FLAG(lcnf1, PCI_HT_LCNF_DFOE));
328 printf("\t\tRevision ID: %u.%02u\n",
329 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
333 lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
334 printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
335 printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
336 FLAG(lfrer0, PCI_HT_LFRER_PROT),
337 FLAG(lfrer0, PCI_HT_LFRER_OV),
338 FLAG(lfrer0, PCI_HT_LFRER_EOC),
339 FLAG(lfrer0, PCI_HT_LFRER_CTLT));
341 lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
342 printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
343 FLAG(lfcap0, PCI_HT_LFCAP_200),
344 FLAG(lfcap0, PCI_HT_LFCAP_300),
345 FLAG(lfcap0, PCI_HT_LFCAP_400),
346 FLAG(lfcap0, PCI_HT_LFCAP_500),
347 FLAG(lfcap0, PCI_HT_LFCAP_600),
348 FLAG(lfcap0, PCI_HT_LFCAP_800),
349 FLAG(lfcap0, PCI_HT_LFCAP_1000),
350 FLAG(lfcap0, PCI_HT_LFCAP_1200),
351 FLAG(lfcap0, PCI_HT_LFCAP_1400),
352 FLAG(lfcap0, PCI_HT_LFCAP_1600),
353 FLAG(lfcap0, PCI_HT_LFCAP_VEND));
355 ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
356 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
357 FLAG(ftr, PCI_HT_FTR_ISOCFC),
358 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
359 FLAG(ftr, PCI_HT_FTR_CRCTM),
360 FLAG(ftr, PCI_HT_FTR_ECTLT),
361 FLAG(ftr, PCI_HT_FTR_64BA),
362 FLAG(ftr, PCI_HT_FTR_UIDRD));
364 lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
365 printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
366 printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
367 FLAG(lfrer1, PCI_HT_LFRER_PROT),
368 FLAG(lfrer1, PCI_HT_LFRER_OV),
369 FLAG(lfrer1, PCI_HT_LFRER_EOC),
370 FLAG(lfrer1, PCI_HT_LFRER_CTLT));
372 lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
373 printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
374 FLAG(lfcap1, PCI_HT_LFCAP_200),
375 FLAG(lfcap1, PCI_HT_LFCAP_300),
376 FLAG(lfcap1, PCI_HT_LFCAP_400),
377 FLAG(lfcap1, PCI_HT_LFCAP_500),
378 FLAG(lfcap1, PCI_HT_LFCAP_600),
379 FLAG(lfcap1, PCI_HT_LFCAP_800),
380 FLAG(lfcap1, PCI_HT_LFCAP_1000),
381 FLAG(lfcap1, PCI_HT_LFCAP_1200),
382 FLAG(lfcap1, PCI_HT_LFCAP_1400),
383 FLAG(lfcap1, PCI_HT_LFCAP_1600),
384 FLAG(lfcap1, PCI_HT_LFCAP_VEND));
386 eh = get_conf_word(d, where + PCI_HT_PRI_EH);
387 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
388 FLAG(eh, PCI_HT_EH_PFLE),
389 FLAG(eh, PCI_HT_EH_OFLE),
390 FLAG(eh, PCI_HT_EH_PFE),
391 FLAG(eh, PCI_HT_EH_OFE),
392 FLAG(eh, PCI_HT_EH_EOCFE),
393 FLAG(eh, PCI_HT_EH_RFE),
394 FLAG(eh, PCI_HT_EH_CRCFE),
395 FLAG(eh, PCI_HT_EH_SERRFE),
396 FLAG(eh, PCI_HT_EH_CF),
397 FLAG(eh, PCI_HT_EH_RE),
398 FLAG(eh, PCI_HT_EH_PNFE),
399 FLAG(eh, PCI_HT_EH_ONFE),
400 FLAG(eh, PCI_HT_EH_EOCNFE),
401 FLAG(eh, PCI_HT_EH_RNFE),
402 FLAG(eh, PCI_HT_EH_CRCNFE),
403 FLAG(eh, PCI_HT_EH_SERRNFE));
405 mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
406 mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
407 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
409 bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
410 printf("\t\tBus Number: %02x\n", bn);
414 cap_ht_sec(struct device *d, int where, int cmd)
416 u16 lctr, lcnf, ftr, eh;
417 u8 rid, lfrer, lfcap, mbu, mlu;
420 printf("HyperTransport: Host or Secondary Interface\n");
424 if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
426 rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
427 if (rid < 0x22 && rid > 0x11)
428 printf("\t\t!!! Possibly incomplete decoding\n");
431 fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
433 fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
435 FLAG(cmd, PCI_HT_SEC_CMD_WR),
436 FLAG(cmd, PCI_HT_SEC_CMD_DE),
437 (cmd & PCI_HT_SEC_CMD_DN) >> 2,
438 FLAG(cmd, PCI_HT_SEC_CMD_CS),
439 FLAG(cmd, PCI_HT_SEC_CMD_HH),
440 FLAG(cmd, PCI_HT_SEC_CMD_AS),
441 FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
442 FLAG(cmd, PCI_HT_SEC_CMD_DUL));
443 lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
445 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
447 fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
449 FLAG(lctr, PCI_HT_LCTR_CFLE),
450 FLAG(lctr, PCI_HT_LCTR_CST),
451 FLAG(lctr, PCI_HT_LCTR_CFE),
452 FLAG(lctr, PCI_HT_LCTR_LKFAIL),
453 FLAG(lctr, PCI_HT_LCTR_INIT),
454 FLAG(lctr, PCI_HT_LCTR_EOC),
455 FLAG(lctr, PCI_HT_LCTR_TXO),
456 (lctr & PCI_HT_LCTR_CRCERR) >> 8,
457 FLAG(lctr, PCI_HT_LCTR_ISOCEN),
458 FLAG(lctr, PCI_HT_LCTR_LSEN),
459 FLAG(lctr, PCI_HT_LCTR_EXTCTL),
460 FLAG(lctr, PCI_HT_LCTR_64B));
461 lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
463 fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
465 fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
467 ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
468 ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
469 ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
470 ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
471 FLAG(lcnf, PCI_HT_LCNF_DFI),
472 FLAG(lcnf, PCI_HT_LCNF_DFO),
473 FLAG(lcnf, PCI_HT_LCNF_DFIE),
474 FLAG(lcnf, PCI_HT_LCNF_DFOE));
475 printf("\t\tRevision ID: %u.%02u\n",
476 (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
479 lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
480 printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
481 printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
482 FLAG(lfrer, PCI_HT_LFRER_PROT),
483 FLAG(lfrer, PCI_HT_LFRER_OV),
484 FLAG(lfrer, PCI_HT_LFRER_EOC),
485 FLAG(lfrer, PCI_HT_LFRER_CTLT));
486 lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
487 printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
488 FLAG(lfcap, PCI_HT_LFCAP_200),
489 FLAG(lfcap, PCI_HT_LFCAP_300),
490 FLAG(lfcap, PCI_HT_LFCAP_400),
491 FLAG(lfcap, PCI_HT_LFCAP_500),
492 FLAG(lfcap, PCI_HT_LFCAP_600),
493 FLAG(lfcap, PCI_HT_LFCAP_800),
494 FLAG(lfcap, PCI_HT_LFCAP_1000),
495 FLAG(lfcap, PCI_HT_LFCAP_1200),
496 FLAG(lfcap, PCI_HT_LFCAP_1400),
497 FLAG(lfcap, PCI_HT_LFCAP_1600),
498 FLAG(lfcap, PCI_HT_LFCAP_VEND));
499 ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
500 printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
501 FLAG(ftr, PCI_HT_FTR_ISOCFC),
502 FLAG(ftr, PCI_HT_FTR_LDTSTOP),
503 FLAG(ftr, PCI_HT_FTR_CRCTM),
504 FLAG(ftr, PCI_HT_FTR_ECTLT),
505 FLAG(ftr, PCI_HT_FTR_64BA),
506 FLAG(ftr, PCI_HT_FTR_UIDRD),
507 FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
508 FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
509 if (ftr & PCI_HT_SEC_FTR_EXTRS)
511 eh = get_conf_word(d, where + PCI_HT_SEC_EH);
512 printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
513 FLAG(eh, PCI_HT_EH_PFLE),
514 FLAG(eh, PCI_HT_EH_OFLE),
515 FLAG(eh, PCI_HT_EH_PFE),
516 FLAG(eh, PCI_HT_EH_OFE),
517 FLAG(eh, PCI_HT_EH_EOCFE),
518 FLAG(eh, PCI_HT_EH_RFE),
519 FLAG(eh, PCI_HT_EH_CRCFE),
520 FLAG(eh, PCI_HT_EH_SERRFE),
521 FLAG(eh, PCI_HT_EH_CF),
522 FLAG(eh, PCI_HT_EH_RE),
523 FLAG(eh, PCI_HT_EH_PNFE),
524 FLAG(eh, PCI_HT_EH_ONFE),
525 FLAG(eh, PCI_HT_EH_EOCNFE),
526 FLAG(eh, PCI_HT_EH_RNFE),
527 FLAG(eh, PCI_HT_EH_CRCNFE),
528 FLAG(eh, PCI_HT_EH_SERRNFE));
529 mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
530 mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
531 printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
536 cap_ht(struct device *d, int where, int cmd)
540 switch (cmd & PCI_HT_CMD_TYP_HI)
542 case PCI_HT_CMD_TYP_HI_PRI:
543 cap_ht_pri(d, where, cmd);
545 case PCI_HT_CMD_TYP_HI_SEC:
546 cap_ht_sec(d, where, cmd);
550 type = cmd & PCI_HT_CMD_TYP;
553 case PCI_HT_CMD_TYP_SW:
554 printf("HyperTransport: Switch\n");
556 case PCI_HT_CMD_TYP_IDC:
557 printf("HyperTransport: Interrupt Discovery and Configuration\n");
559 case PCI_HT_CMD_TYP_RID:
560 printf("HyperTransport: Revision ID: %u.%02u\n",
561 (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
563 case PCI_HT_CMD_TYP_UIDC:
564 printf("HyperTransport: UnitID Clumping\n");
566 case PCI_HT_CMD_TYP_ECSA:
567 printf("HyperTransport: Extended Configuration Space Access\n");
569 case PCI_HT_CMD_TYP_AM:
570 printf("HyperTransport: Address Mapping\n");
572 case PCI_HT_CMD_TYP_MSIM:
573 printf("HyperTransport: MSI Mapping Enable%c Fixed%c\n",
574 FLAG(cmd, PCI_HT_MSIM_CMD_EN),
575 FLAG(cmd, PCI_HT_MSIM_CMD_FIXD));
576 if (verbose >= 2 && !(cmd & PCI_HT_MSIM_CMD_FIXD))
579 if (!config_fetch(d, where + PCI_HT_MSIM_ADDR_LO, 8))
581 offl = get_conf_long(d, where + PCI_HT_MSIM_ADDR_LO);
582 offh = get_conf_long(d, where + PCI_HT_MSIM_ADDR_HI);
583 printf("\t\tMapping Address Base: %016" PCI_U64_FMT_X "\n", ((u64)offh << 32) | (offl & ~0xfffff));
586 case PCI_HT_CMD_TYP_DR:
587 printf("HyperTransport: DirectRoute\n");
589 case PCI_HT_CMD_TYP_VCS:
590 printf("HyperTransport: VCSet\n");
592 case PCI_HT_CMD_TYP_RM:
593 printf("HyperTransport: Retry Mode\n");
595 case PCI_HT_CMD_TYP_X86:
596 printf("HyperTransport: X86 (reserved)\n");
599 printf("HyperTransport: #%02x\n", type >> 11);
604 cap_msi(struct device *d, int where, int cap)
610 printf("MSI: Enable%c Count=%d/%d Maskable%c 64bit%c\n",
611 FLAG(cap, PCI_MSI_FLAGS_ENABLE),
612 1 << ((cap & PCI_MSI_FLAGS_QSIZE) >> 4),
613 1 << ((cap & PCI_MSI_FLAGS_QMASK) >> 1),
614 FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
615 FLAG(cap, PCI_MSI_FLAGS_64BIT));
618 is64 = cap & PCI_MSI_FLAGS_64BIT;
619 if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
621 printf("\t\tAddress: ");
624 t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
625 w = get_conf_word(d, where + PCI_MSI_DATA_64);
629 w = get_conf_word(d, where + PCI_MSI_DATA_32);
630 t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
631 printf("%08x Data: %04x\n", t, w);
632 if (cap & PCI_MSI_FLAGS_MASK_BIT)
638 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_64, 8))
640 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_64);
641 pending = get_conf_long(d, where + PCI_MSI_PENDING_64);
645 if (!config_fetch(d, where + PCI_MSI_MASK_BIT_32, 8))
647 mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_32);
648 pending = get_conf_long(d, where + PCI_MSI_PENDING_32);
650 printf("\t\tMasking: %08x Pending: %08x\n", mask, pending);
654 static int exp_downstream_port(int type)
656 return type == PCI_EXP_TYPE_ROOT_PORT ||
657 type == PCI_EXP_TYPE_DOWNSTREAM ||
658 type == PCI_EXP_TYPE_PCIE_BRIDGE; /* PCI/PCI-X to PCIe Bridge */
661 static void show_power_limit(int value, int scale)
663 static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
665 if (scale == 0 && value == 0xFF)
671 if (scale == 0 && value >= 0xF0 && value <= 0xFE)
672 value = 250 + 25 * (value - 0xF0);
674 printf("%gW", value * scales[scale]);
677 static const char *latency_l0s(int value)
679 static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
680 return latencies[value];
683 static const char *latency_l1(int value)
685 static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
686 return latencies[value];
689 static void cap_express_dev(struct device *d, int where, int type)
694 t = get_conf_long(d, where + PCI_EXP_DEVCAP);
695 printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d",
696 128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
697 (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1);
698 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END))
699 printf(", Latency L0s %s, L1 %s",
700 latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
701 latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
703 printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
704 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
705 (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
706 printf(" AttnBtn%c AttnInd%c PwrInd%c",
707 FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
708 FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
710 FLAG(t, PCI_EXP_DEVCAP_RBE));
711 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_ROOT_INT_EP))
713 FLAG(t, PCI_EXP_DEVCAP_FLRESET));
714 if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_UPSTREAM) ||
715 (type == PCI_EXP_TYPE_PCI_BRIDGE))
717 printf(" SlotPowerLimit ");
718 show_power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18, (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26);
722 w = get_conf_word(d, where + PCI_EXP_DEVCTL);
723 printf("\t\tDevCtl:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c\n",
724 FLAG(w, PCI_EXP_DEVCTL_CERE),
725 FLAG(w, PCI_EXP_DEVCTL_NFERE),
726 FLAG(w, PCI_EXP_DEVCTL_FERE),
727 FLAG(w, PCI_EXP_DEVCTL_URRE));
728 printf("\t\t\tRlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c",
729 FLAG(w, PCI_EXP_DEVCTL_RELAXED),
730 FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
731 FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
732 FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
733 FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
734 if (type == PCI_EXP_TYPE_PCI_BRIDGE)
735 printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE));
736 if (((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_ROOT_INT_EP)) &&
737 (t & PCI_EXP_DEVCAP_FLRESET))
738 printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET));
739 printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
740 128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
741 128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
743 w = get_conf_word(d, where + PCI_EXP_DEVSTA);
744 printf("\t\tDevSta:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c AuxPwr%c TransPend%c\n",
745 FLAG(w, PCI_EXP_DEVSTA_CED),
746 FLAG(w, PCI_EXP_DEVSTA_NFED),
747 FLAG(w, PCI_EXP_DEVSTA_FED),
748 FLAG(w, PCI_EXP_DEVSTA_URD),
749 FLAG(w, PCI_EXP_DEVSTA_AUXPD),
750 FLAG(w, PCI_EXP_DEVSTA_TRPND));
753 static char *link_speed(int speed)
774 static char *link_compare(int type, int sta, int cap)
777 return " (overdriven)";
780 if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_DOWNSTREAM) ||
781 (type == PCI_EXP_TYPE_PCIE_BRIDGE))
783 return " (downgraded)";
786 static char *aspm_support(int code)
791 return "not supported";
803 static const char *aspm_enabled(int code)
805 static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
809 static void cap_express_link(struct device *d, int where, int type)
811 u32 t, aspm, cap_speed, cap_width, sta_speed, sta_width;
814 t = get_conf_long(d, where + PCI_EXP_LNKCAP);
815 aspm = (t & PCI_EXP_LNKCAP_ASPM) >> 10;
816 cap_speed = t & PCI_EXP_LNKCAP_SPEED;
817 cap_width = (t & PCI_EXP_LNKCAP_WIDTH) >> 4;
818 printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s",
820 link_speed(cap_speed), cap_width,
824 printf(", Exit Latency ");
826 printf("L0s %s", latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12));
828 printf("%sL1 %s", (aspm & 1) ? ", " : "",
829 latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
832 printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c ASPMOptComp%c\n",
833 FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
834 FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
835 FLAG(t, PCI_EXP_LNKCAP_DLLA),
836 FLAG(t, PCI_EXP_LNKCAP_LBNC),
837 FLAG(t, PCI_EXP_LNKCAP_AOC));
839 w = get_conf_word(d, where + PCI_EXP_LNKCTL);
840 printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
841 if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
842 (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
843 printf(" RCB %d bytes,", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
844 printf(" Disabled%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
845 FLAG(w, PCI_EXP_LNKCTL_DISABLE),
846 FLAG(w, PCI_EXP_LNKCTL_CLOCK),
847 FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
848 FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
849 FLAG(w, PCI_EXP_LNKCTL_HWAUTWD),
850 FLAG(w, PCI_EXP_LNKCTL_BWMIE),
851 FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
853 w = get_conf_word(d, where + PCI_EXP_LNKSTA);
854 sta_speed = w & PCI_EXP_LNKSTA_SPEED;
855 sta_width = (w & PCI_EXP_LNKSTA_WIDTH) >> 4;
856 printf("\t\tLnkSta:\tSpeed %s%s, Width x%d%s\n",
857 link_speed(sta_speed),
858 link_compare(type, sta_speed, cap_speed),
860 link_compare(type, sta_width, cap_width));
861 printf("\t\t\tTrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
862 FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
863 FLAG(w, PCI_EXP_LNKSTA_TRAIN),
864 FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
865 FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
866 FLAG(w, PCI_EXP_LNKSTA_BWMGMT),
867 FLAG(w, PCI_EXP_LNKSTA_AUTBW));
870 static const char *indicator(int code)
872 static const char *names[] = { "Unknown", "On", "Blink", "Off" };
876 static void cap_express_slot(struct device *d, int where)
881 t = get_conf_long(d, where + PCI_EXP_SLTCAP);
882 printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c\n",
883 FLAG(t, PCI_EXP_SLTCAP_ATNB),
884 FLAG(t, PCI_EXP_SLTCAP_PWRC),
885 FLAG(t, PCI_EXP_SLTCAP_MRL),
886 FLAG(t, PCI_EXP_SLTCAP_ATNI),
887 FLAG(t, PCI_EXP_SLTCAP_PWRI),
888 FLAG(t, PCI_EXP_SLTCAP_HPC),
889 FLAG(t, PCI_EXP_SLTCAP_HPS));
890 printf("\t\t\tSlot #%d, PowerLimit ",
891 (t & PCI_EXP_SLTCAP_PSN) >> 19);
892 show_power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15);
893 printf("; Interlock%c NoCompl%c\n",
894 FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
895 FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP));
897 w = get_conf_word(d, where + PCI_EXP_SLTCTL);
898 printf("\t\tSltCtl:\tEnable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c\n",
899 FLAG(w, PCI_EXP_SLTCTL_ATNB),
900 FLAG(w, PCI_EXP_SLTCTL_PWRF),
901 FLAG(w, PCI_EXP_SLTCTL_MRLS),
902 FLAG(w, PCI_EXP_SLTCTL_PRSD),
903 FLAG(w, PCI_EXP_SLTCTL_CMDC),
904 FLAG(w, PCI_EXP_SLTCTL_HPIE),
905 FLAG(w, PCI_EXP_SLTCTL_LLCHG));
906 printf("\t\t\tControl: AttnInd %s, PwrInd %s, Power%c Interlock%c\n",
907 indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
908 indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
909 FLAG(w, PCI_EXP_SLTCTL_PWRC),
910 FLAG(w, PCI_EXP_SLTCTL_INTERLOCK));
912 w = get_conf_word(d, where + PCI_EXP_SLTSTA);
913 printf("\t\tSltSta:\tStatus: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c\n",
914 FLAG(w, PCI_EXP_SLTSTA_ATNB),
915 FLAG(w, PCI_EXP_SLTSTA_PWRF),
916 FLAG(w, PCI_EXP_SLTSTA_MRL_ST),
917 FLAG(w, PCI_EXP_SLTSTA_CMDC),
918 FLAG(w, PCI_EXP_SLTSTA_PRES),
919 FLAG(w, PCI_EXP_SLTSTA_INTERLOCK));
920 printf("\t\t\tChanged: MRL%c PresDet%c LinkState%c\n",
921 FLAG(w, PCI_EXP_SLTSTA_MRLS),
922 FLAG(w, PCI_EXP_SLTSTA_PRSD),
923 FLAG(w, PCI_EXP_SLTSTA_LLCHG));
926 static void cap_express_root(struct device *d, int where)
930 w = get_conf_word(d, where + PCI_EXP_RTCAP);
931 printf("\t\tRootCap: CRSVisible%c\n",
932 FLAG(w, PCI_EXP_RTCAP_CRSVIS));
934 w = get_conf_word(d, where + PCI_EXP_RTCTL);
935 printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n",
936 FLAG(w, PCI_EXP_RTCTL_SECEE),
937 FLAG(w, PCI_EXP_RTCTL_SENFEE),
938 FLAG(w, PCI_EXP_RTCTL_SEFEE),
939 FLAG(w, PCI_EXP_RTCTL_PMEIE),
940 FLAG(w, PCI_EXP_RTCTL_CRSVIS));
942 w = get_conf_long(d, where + PCI_EXP_RTSTA);
943 printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
944 w & PCI_EXP_RTSTA_PME_REQID,
945 FLAG(w, PCI_EXP_RTSTA_PME_STATUS),
946 FLAG(w, PCI_EXP_RTSTA_PME_PENDING));
949 static const char *cap_express_dev2_timeout_range(int type)
951 /* Decode Completion Timeout Ranges. */
955 return "Not Supported";
975 static const char *cap_express_dev2_timeout_value(int type)
977 /* Decode Completion Timeout Value. */
981 return "50us to 50ms";
983 return "50us to 100us";
985 return "1ms to 10ms";
987 return "16ms to 55ms";
989 return "65ms to 210ms";
991 return "260ms to 900ms";
1003 static const char *cap_express_devcap2_obff(int obff)
1008 return "Via message";
1012 return "Via message/WAKE#";
1014 return "Not Supported";
1018 static const char *cap_express_devcap2_epr(int epr)
1023 return "Dev Specific";
1025 return "Form Factor Dev Specific";
1029 return "Not Supported";
1033 static const char *cap_express_devcap2_lncls(int lncls)
1038 return "64byte cachelines";
1040 return "128byte cachelines";
1044 return "Not Supported";
1048 static const char *cap_express_devcap2_tphcomp(int tph)
1053 return "TPHComp+ ExtTPHComp-";
1055 /* Reserved; intentionally left blank */
1058 return "TPHComp+ ExtTPHComp+";
1060 return "TPHComp- ExtTPHComp-";
1064 static const char *cap_express_devctl2_obff(int obff)
1071 return "Via message A";
1073 return "Via message B";
1082 device_has_memory_space_bar(struct device *d)
1084 struct pci_dev *p = d->dev;
1088 if (p->base_addr[i] || p->size[i])
1090 if (!(p->base_addr[i] & PCI_BASE_ADDRESS_SPACE_IO))
1099 static void cap_express_dev2(struct device *d, int where, int type)
1103 int has_mem_bar = device_has_memory_space_bar(d);
1105 l = get_conf_long(d, where + PCI_EXP_DEVCAP2);
1106 printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c NROPrPrP%c LTR%c",
1107 cap_express_dev2_timeout_range(PCI_EXP_DEVCAP2_TIMEOUT_RANGE(l)),
1108 FLAG(l, PCI_EXP_DEVCAP2_TIMEOUT_DIS),
1109 FLAG(l, PCI_EXP_DEVCAP2_NROPRPRP),
1110 FLAG(l, PCI_EXP_DEVCAP2_LTR));
1111 printf("\n\t\t\t 10BitTagComp%c 10BitTagReq%c OBFF %s, ExtFmt%c EETLPPrefix%c",
1112 FLAG(l, PCI_EXP_DEVCAP2_10BIT_TAG_COMP),
1113 FLAG(l, PCI_EXP_DEVCAP2_10BIT_TAG_REQ),
1114 cap_express_devcap2_obff(PCI_EXP_DEVCAP2_OBFF(l)),
1115 FLAG(l, PCI_EXP_DEVCAP2_EXTFMT),
1116 FLAG(l, PCI_EXP_DEVCAP2_EE_TLP));
1118 if (PCI_EXP_DEVCAP2_EE_TLP == (l & PCI_EXP_DEVCAP2_EE_TLP))
1120 printf(", MaxEETLPPrefixes %d",
1121 PCI_EXP_DEVCAP2_MEE_TLP(l) ? PCI_EXP_DEVCAP2_MEE_TLP(l) : 4);
1124 printf("\n\t\t\t EmergencyPowerReduction %s, EmergencyPowerReductionInit%c",
1125 cap_express_devcap2_epr(PCI_EXP_DEVCAP2_EPR(l)),
1126 FLAG(l, PCI_EXP_DEVCAP2_EPR_INIT));
1127 printf("\n\t\t\t FRS%c", FLAG(l, PCI_EXP_DEVCAP2_FRS));
1129 if (type == PCI_EXP_TYPE_ROOT_PORT)
1130 printf(" LN System CLS %s,",
1131 cap_express_devcap2_lncls(PCI_EXP_DEVCAP2_LN_CLS(l)));
1133 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT)
1134 printf(" %s", cap_express_devcap2_tphcomp(PCI_EXP_DEVCAP2_TPH_COMP(l)));
1136 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
1137 printf(" ARIFwd%c\n", FLAG(l, PCI_EXP_DEVCAP2_ARI));
1140 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1141 type == PCI_EXP_TYPE_DOWNSTREAM || has_mem_bar)
1143 printf("\t\t\t AtomicOpsCap:");
1144 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1145 type == PCI_EXP_TYPE_DOWNSTREAM)
1146 printf(" Routing%c", FLAG(l, PCI_EXP_DEVCAP2_ATOMICOP_ROUTING));
1147 if (type == PCI_EXP_TYPE_ROOT_PORT || has_mem_bar)
1148 printf(" 32bit%c 64bit%c 128bitCAS%c",
1149 FLAG(l, PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP),
1150 FLAG(l, PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP),
1151 FLAG(l, PCI_EXP_DEVCAP2_128BIT_CAS_COMP));
1155 w = get_conf_word(d, where + PCI_EXP_DEVCTL2);
1156 printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c",
1157 cap_express_dev2_timeout_value(PCI_EXP_DEVCTL2_TIMEOUT_VALUE(w)),
1158 FLAG(w, PCI_EXP_DEVCTL2_TIMEOUT_DIS));
1159 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
1160 printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEVCTL2_ARI));
1163 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1164 type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ENDPOINT ||
1165 type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
1167 printf("\t\t\t AtomicOpsCtl:");
1168 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT ||
1169 type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
1170 printf(" ReqEn%c", FLAG(w, PCI_EXP_DEVCTL2_ATOMICOP_REQUESTER_EN));
1171 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1172 type == PCI_EXP_TYPE_DOWNSTREAM)
1173 printf(" EgressBlck%c", FLAG(w, PCI_EXP_DEVCTL2_ATOMICOP_EGRESS_BLOCK));
1176 printf("\t\t\t LTR%c 10BitTagReq%c OBFF %s\n",
1177 FLAG(w, PCI_EXP_DEVCTL2_LTR),
1178 FLAG(w, PCI_EXP_DEVCTL2_10BIT_TAG_REQ),
1179 cap_express_devctl2_obff(PCI_EXP_DEVCTL2_OBFF(w)));
1182 static const char *cap_express_link2_speed_cap(int vector)
1185 * Per PCIe r5.0, sec 8.2.1, a device must support 2.5GT/s and is not
1186 * permitted to skip support for any data rates between 2.5GT/s and the
1187 * highest supported rate.
1192 return "2.5-32GT/s";
1194 return "2.5-16GT/s";
1205 static const char *cap_express_link2_speed(int type)
1209 case 0: /* hardwire to 0 means only the 2.5GT/s is supported */
1227 static const char *cap_express_link2_deemphasis(int type)
1240 static const char *cap_express_link2_compliance_preset(int type)
1245 return "-6dB de-emphasis, 0dB preshoot";
1247 return "-3.5dB de-emphasis, 0dB preshoot";
1249 return "-4.4dB de-emphasis, 0dB preshoot";
1251 return "-2.5dB de-emphasis, 0dB preshoot";
1253 return "0dB de-emphasis, 0dB preshoot";
1255 return "0dB de-emphasis, 1.9dB preshoot";
1257 return "0dB de-emphasis, 2.5dB preshoot";
1259 return "-6.0dB de-emphasis, 3.5dB preshoot";
1261 return "-3.5dB de-emphasis, 3.5dB preshoot";
1263 return "0dB de-emphasis, 3.5dB preshoot";
1269 static const char *cap_express_link2_transmargin(int type)
1274 return "Normal Operating Range";
1276 return "800-1200mV(full-swing)/400-700mV(half-swing)";
1281 return "200-400mV(full-swing)/100-200mV(half-swing)";
1287 static const char *cap_express_link2_crosslink_res(int crosslink)
1292 return "unsupported";
1294 return "Upstream Port";
1296 return "Downstream Port";
1298 return "incomplete";
1302 static const char *cap_express_link2_component(int presence)
1307 return "Link Down - Not Determined";
1309 return "Link Down - Not Present";
1311 return "Link Down - Present";
1313 return "Link Up - Present";
1315 return "Link Up - Present and DRS Received";
1321 static void cap_express_link2(struct device *d, int where, int type)
1326 if (!((type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_LEG_END) &&
1327 (d->dev->dev != 0 || d->dev->func != 0))) {
1328 /* Link Capabilities 2 was reserved before PCIe r3.0 */
1329 l = get_conf_long(d, where + PCI_EXP_LNKCAP2);
1331 printf("\t\tLnkCap2: Supported Link Speeds: %s, Crosslink%c "
1332 "Retimer%c 2Retimers%c DRS%c\n",
1333 cap_express_link2_speed_cap(PCI_EXP_LNKCAP2_SPEED(l)),
1334 FLAG(l, PCI_EXP_LNKCAP2_CROSSLINK),
1335 FLAG(l, PCI_EXP_LNKCAP2_RETIMER),
1336 FLAG(l, PCI_EXP_LNKCAP2_2RETIMERS),
1337 FLAG(l, PCI_EXP_LNKCAP2_DRS));
1340 w = get_conf_word(d, where + PCI_EXP_LNKCTL2);
1341 printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c",
1342 cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w)),
1343 FLAG(w, PCI_EXP_LNKCTL2_CMPLNC),
1344 FLAG(w, PCI_EXP_LNKCTL2_SPEED_DIS));
1345 if (type == PCI_EXP_TYPE_DOWNSTREAM)
1346 printf(", Selectable De-emphasis: %s",
1347 cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w)));
1349 "\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n"
1350 "\t\t\t Compliance Preset/De-emphasis: %s\n",
1351 cap_express_link2_transmargin(PCI_EXP_LNKCTL2_MARGIN(w)),
1352 FLAG(w, PCI_EXP_LNKCTL2_MOD_CMPLNC),
1353 FLAG(w, PCI_EXP_LNKCTL2_CMPLNC_SOS),
1354 cap_express_link2_compliance_preset(PCI_EXP_LNKCTL2_COM_DEEMPHASIS(w)));
1357 w = get_conf_word(d, where + PCI_EXP_LNKSTA2);
1358 printf("\t\tLnkSta2: Current De-emphasis Level: %s, EqualizationComplete%c EqualizationPhase1%c\n"
1359 "\t\t\t EqualizationPhase2%c EqualizationPhase3%c LinkEqualizationRequest%c\n"
1360 "\t\t\t Retimer%c 2Retimers%c CrosslinkRes: %s",
1361 cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)),
1362 FLAG(w, PCI_EXP_LINKSTA2_EQU_COMP),
1363 FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE1),
1364 FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE2),
1365 FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE3),
1366 FLAG(w, PCI_EXP_LINKSTA2_EQU_REQ),
1367 FLAG(w, PCI_EXP_LINKSTA2_RETIMER),
1368 FLAG(w, PCI_EXP_LINKSTA2_2RETIMERS),
1369 cap_express_link2_crosslink_res(PCI_EXP_LINKSTA2_CROSSLINK(w)));
1371 if (exp_downstream_port(type) && (l & PCI_EXP_LNKCAP2_DRS)) {
1373 "\t\t\t DownstreamComp: %s\n",
1374 FLAG(w, PCI_EXP_LINKSTA2_DRS_RCVD),
1375 cap_express_link2_component(PCI_EXP_LINKSTA2_COMPONENT(w)));
1380 static void cap_express_slot2(struct device *d UNUSED, int where UNUSED)
1382 /* No capabilities that require this field in PCIe rev2.0 spec. */
1386 cap_express(struct device *d, int where, int cap)
1388 int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1395 printf("(v%d) ", cap & PCI_EXP_FLAGS_VERS);
1398 case PCI_EXP_TYPE_ENDPOINT:
1401 case PCI_EXP_TYPE_LEG_END:
1402 printf("Legacy Endpoint");
1404 case PCI_EXP_TYPE_ROOT_PORT:
1405 slot = cap & PCI_EXP_FLAGS_SLOT;
1406 printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1408 case PCI_EXP_TYPE_UPSTREAM:
1409 printf("Upstream Port");
1411 case PCI_EXP_TYPE_DOWNSTREAM:
1412 slot = cap & PCI_EXP_FLAGS_SLOT;
1413 printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1415 case PCI_EXP_TYPE_PCI_BRIDGE:
1416 printf("PCI-Express to PCI/PCI-X Bridge");
1418 case PCI_EXP_TYPE_PCIE_BRIDGE:
1419 slot = cap & PCI_EXP_FLAGS_SLOT;
1420 printf("PCI/PCI-X to PCI-Express Bridge (Slot%c)",
1421 FLAG(cap, PCI_EXP_FLAGS_SLOT));
1423 case PCI_EXP_TYPE_ROOT_INT_EP:
1425 printf("Root Complex Integrated Endpoint");
1427 case PCI_EXP_TYPE_ROOT_EC:
1429 printf("Root Complex Event Collector");
1432 printf("Unknown type %d", type);
1434 printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1441 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC)
1443 if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1446 cap_express_dev(d, where, type);
1448 cap_express_link(d, where, type);
1450 cap_express_slot(d, where);
1451 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC)
1452 cap_express_root(d, where);
1454 if ((cap & PCI_EXP_FLAGS_VERS) < 2)
1460 if (!config_fetch(d, where + PCI_EXP_DEVCAP2, size))
1463 cap_express_dev2(d, where, type);
1465 cap_express_link2(d, where, type);
1467 cap_express_slot2(d, where);
1472 cap_msix(struct device *d, int where, int cap)
1476 printf("MSI-X: Enable%c Count=%d Masked%c\n",
1477 FLAG(cap, PCI_MSIX_ENABLE),
1478 (cap & PCI_MSIX_TABSIZE) + 1,
1479 FLAG(cap, PCI_MSIX_MASK));
1480 if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1483 off = get_conf_long(d, where + PCI_MSIX_TABLE);
1484 printf("\t\tVector table: BAR=%d offset=%08x\n",
1485 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1486 off = get_conf_long(d, where + PCI_MSIX_PBA);
1487 printf("\t\tPBA: BAR=%d offset=%08x\n",
1488 off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1494 int esr = cap & 0xff;
1497 printf("Slot ID: %d slots, First%c, chassis %02x\n",
1498 esr & PCI_SID_ESR_NSLOTS,
1499 FLAG(esr, PCI_SID_ESR_FIC),
1504 cap_ssvid(struct device *d, int where)
1506 u16 subsys_v, subsys_d;
1507 char ssnamebuf[256];
1509 if (!config_fetch(d, where, 8))
1511 subsys_v = get_conf_word(d, where + PCI_SSVID_VENDOR);
1512 subsys_d = get_conf_word(d, where + PCI_SSVID_DEVICE);
1513 printf("Subsystem: %s\n",
1514 pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1515 PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1516 d->dev->vendor_id, d->dev->device_id, subsys_v, subsys_d));
1520 cap_debug_port(int cap)
1522 int bar = cap >> 13;
1523 int pos = cap & 0x1fff;
1524 printf("Debug port: BAR=%d offset=%04x\n", bar, pos);
1528 cap_af(struct device *d, int where)
1532 printf("PCI Advanced Features\n");
1533 if (verbose < 2 || !config_fetch(d, where + PCI_AF_CAP, 3))
1536 reg = get_conf_byte(d, where + PCI_AF_CAP);
1537 printf("\t\tAFCap: TP%c FLR%c\n", FLAG(reg, PCI_AF_CAP_TP),
1538 FLAG(reg, PCI_AF_CAP_FLR));
1539 reg = get_conf_byte(d, where + PCI_AF_CTRL);
1540 printf("\t\tAFCtrl: FLR%c\n", FLAG(reg, PCI_AF_CTRL_FLR));
1541 reg = get_conf_byte(d, where + PCI_AF_STATUS);
1542 printf("\t\tAFStatus: TP%c\n", FLAG(reg, PCI_AF_STATUS_TP));
1546 cap_sata_hba(struct device *d, int where, int cap)
1551 printf("SATA HBA v%d.%d", BITS(cap, 4, 4), BITS(cap, 0, 4));
1552 if (verbose < 2 || !config_fetch(d, where + PCI_SATA_HBA_BARS, 4))
1558 bars = get_conf_long(d, where + PCI_SATA_HBA_BARS);
1559 bar = BITS(bars, 0, 4);
1560 if (bar >= 4 && bar <= 9)
1561 printf(" BAR%d Offset=%08x\n", bar - 4, BITS(bars, 4, 20));
1563 printf(" InCfgSpace\n");
1565 printf(" BAR??%d\n", bar);
1568 static const char *cap_ea_property(int p, int is_secondary)
1572 return "memory space, non-prefetchable";
1574 return "memory space, prefetchable";
1578 return "VF memory space, prefetchable";
1580 return "VF memory space, non-prefetchable";
1582 return "allocation behind bridge, non-prefetchable memory";
1584 return "allocation behind bridge, prefetchable memory";
1586 return "allocation behind bridge, I/O space";
1588 return "memory space resource unavailable for use";
1590 return "I/O space resource unavailable for use";
1593 return "entry unavailable for use, PrimaryProperties should be used";
1595 return "entry unavailable for use";
1601 static void cap_ea(struct device *d, int where, int cap)
1604 int entry_base = where + 4;
1605 int num_entries = BITS(cap, 0, 6);
1606 u8 htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1608 printf("Enhanced Allocation (EA): NumEntries=%u", num_entries);
1609 if (htype == PCI_HEADER_TYPE_BRIDGE) {
1610 byte fixed_sub, fixed_sec;
1613 if (!config_fetch(d, where + 4, 2)) {
1617 fixed_sec = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SECONDARY);
1618 fixed_sub = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SUBORDINATE);
1619 printf(", secondary=%d, subordinate=%d", fixed_sec, fixed_sub);
1625 for (entry = 0; entry < num_entries; entry++) {
1626 int max_offset_high_pos, has_base_high, has_max_offset_high;
1628 u32 base, max_offset;
1629 int es, bei, pp, sp;
1630 const char *prop_text;
1632 if (!config_fetch(d, entry_base, 4))
1634 entry_header = get_conf_long(d, entry_base);
1635 es = BITS(entry_header, 0, 3);
1636 bei = BITS(entry_header, 4, 4);
1637 pp = BITS(entry_header, 8, 8);
1638 sp = BITS(entry_header, 16, 8);
1639 if (!config_fetch(d, entry_base + 4, es * 4))
1641 printf("\t\tEntry %u: Enable%c Writable%c EntrySize=%u\n", entry,
1642 FLAG(entry_header, PCI_EA_CAP_ENT_ENABLE),
1643 FLAG(entry_header, PCI_EA_CAP_ENT_WRITABLE), es);
1644 printf("\t\t\t BAR Equivalent Indicator: ");
1652 printf("BAR %u", bei);
1655 printf("resource behind function");
1658 printf("not indicated");
1661 printf("expansion ROM");
1669 printf("VF-BAR %u", bei - 9);
1677 prop_text = cap_ea_property(pp, 0);
1678 printf("\t\t\t PrimaryProperties: ");
1680 printf("%s\n", prop_text);
1682 printf("[%02x]\n", pp);
1684 prop_text = cap_ea_property(sp, 1);
1685 printf("\t\t\t SecondaryProperties: ");
1687 printf("%s\n", prop_text);
1689 printf("[%02x]\n", sp);
1691 base = get_conf_long(d, entry_base + 4);
1692 has_base_high = ((base & 2) != 0);
1695 max_offset = get_conf_long(d, entry_base + 8);
1696 has_max_offset_high = ((max_offset & 2) != 0);
1698 max_offset_high_pos = entry_base + 12;
1700 printf("\t\t\t Base: ");
1701 if (has_base_high) {
1702 u32 base_high = get_conf_long(d, entry_base + 12);
1704 printf("%x", base_high);
1705 max_offset_high_pos += 4;
1707 printf("%08x\n", base);
1709 printf("\t\t\t MaxOffset: ");
1710 if (has_max_offset_high) {
1711 u32 max_offset_high = get_conf_long(d, max_offset_high_pos);
1713 printf("%x", max_offset_high);
1715 printf("%08x\n", max_offset);
1717 entry_base += 4 + 4 * es;
1722 show_caps(struct device *d, int where)
1724 int can_have_ext_caps = 0;
1727 if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1729 byte been_there[256];
1730 where = get_conf_byte(d, where) & ~3;
1731 memset(been_there, 0, 256);
1735 printf("\tCapabilities: ");
1736 if (!config_fetch(d, where, 4))
1738 puts("<access denied>");
1741 id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1742 next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1743 cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1744 printf("[%02x] ", where);
1745 if (been_there[where]++)
1747 printf("<chain looped>\n");
1752 printf("<chain broken>\n");
1757 case PCI_CAP_ID_NULL:
1761 cap_pm(d, where, cap);
1763 case PCI_CAP_ID_AGP:
1764 cap_agp(d, where, cap);
1766 case PCI_CAP_ID_VPD:
1769 case PCI_CAP_ID_SLOTID:
1772 case PCI_CAP_ID_MSI:
1773 cap_msi(d, where, cap);
1775 case PCI_CAP_ID_CHSWP:
1776 printf("CompactPCI hot-swap <?>\n");
1778 case PCI_CAP_ID_PCIX:
1780 can_have_ext_caps = 1;
1783 cap_ht(d, where, cap);
1785 case PCI_CAP_ID_VNDR:
1786 show_vendor_caps(d, where, cap);
1788 case PCI_CAP_ID_DBG:
1789 cap_debug_port(cap);
1791 case PCI_CAP_ID_CCRC:
1792 printf("CompactPCI central resource control <?>\n");
1794 case PCI_CAP_ID_HOTPLUG:
1795 printf("Hot-plug capable\n");
1797 case PCI_CAP_ID_SSVID:
1798 cap_ssvid(d, where);
1800 case PCI_CAP_ID_AGP3:
1801 printf("AGP3 <?>\n");
1803 case PCI_CAP_ID_SECURE:
1804 printf("Secure device <?>\n");
1806 case PCI_CAP_ID_EXP:
1807 type = cap_express(d, where, cap);
1808 can_have_ext_caps = 1;
1810 case PCI_CAP_ID_MSIX:
1811 cap_msix(d, where, cap);
1813 case PCI_CAP_ID_SATA:
1814 cap_sata_hba(d, where, cap);
1820 cap_ea(d, where, cap);
1823 printf("Capability ID %#02x [%04x]\n", id, cap);
1828 if (can_have_ext_caps)
1829 show_ext_caps(d, type);