2 * The PCI Utilities -- Log margining process
4 * Copyright (c) 2023 KNS Group LLC (YADRO)
6 * Can be freely distributed and used under the terms of the GNU GPL v2+.
8 * SPDX-License-Identifier: GPL-2.0-or-later
16 bool margin_global_logging = false;
17 bool margin_print_domain = true;
20 margin_log(char *format, ...)
23 va_start(arg, format);
24 if (margin_global_logging)
30 margin_log_bdfs(struct pci_dev *down, struct pci_dev *up)
32 if (margin_print_domain)
33 margin_log("%x:%x:%x.%x -> %x:%x:%x.%x", down->domain, down->bus, down->dev, down->func,
34 up->domain, up->bus, up->dev, up->func);
36 margin_log("%x:%x.%x -> %x:%x.%x", down->bus, down->dev, down->func, up->bus, up->dev,
41 margin_log_link(struct margin_link *link)
44 margin_log_bdfs(link->down_port.dev, link->up_port.dev);
45 margin_log("\nNegotiated Link Width: %d\n", link->down_port.width);
46 margin_log("Link Speed: %d.0 GT/s = Gen %d\n", (link->down_port.link_speed - 3) * 16,
47 link->down_port.link_speed);
48 margin_log("Available receivers: ");
49 int receivers_n = 2 + 2 * link->down_port.retimers_n;
50 for (int i = 1; i < receivers_n; i++)
51 margin_log("Rx(%X) - %d, ", 10 + i - 1, i);
52 margin_log("Rx(F) - 6\n");
56 margin_log_params(struct margin_params *params)
58 margin_log("Independent Error Sampler: %d\n", params->ind_error_sampler);
59 margin_log("Sample Reporting Method: %d\n", params->sample_report_method);
60 margin_log("Independent Left and Right Timing Margining: %d\n", params->ind_left_right_tim);
61 margin_log("Voltage Margining Supported: %d\n", params->volt_support);
62 margin_log("Independent Up and Down Voltage Margining: %d\n", params->ind_up_down_volt);
63 margin_log("Number of Timing Steps: %d\n", params->timing_steps);
64 margin_log("Number of Voltage Steps: %d\n", params->volt_steps);
65 margin_log("Max Timing Offset: %d\n", params->timing_offset);
66 margin_log("Max Voltage Offset: %d\n", params->volt_offset);
67 margin_log("Max Lanes: %d\n", params->max_lanes);
71 margin_log_recvn(struct margin_recv *recv)
73 margin_log("\nReceiver = Rx(%X)\n", 10 + recv->recvn - 1);
77 margin_log_receiver(struct margin_recv *recv)
79 margin_log("\nError Count Limit = %d\n", recv->error_limit);
80 margin_log("Parallel Lanes: %d\n\n", recv->parallel_lanes);
82 margin_log_params(recv->params);
84 if (recv->lane_reversal)
86 margin_log("\nWarning: device uses Lane Reversal.\n");
87 margin_log("However, utility uses logical lane numbers in arguments and for logging.\n");
90 if (recv->params->timing_offset == 0)
91 margin_log("\nWarning: Vendor chose not to report the Max Timing Offset.\n"
92 "Utility will use its max possible value - 50 (50%% UI).\n");
93 if (recv->params->volt_support && recv->params->volt_offset == 0)
94 margin_log("\nWarning: Vendor chose not to report the Max Voltage Offset.\n"
95 "Utility will use its max possible value - 50 (500 mV).\n");
99 margin_log_margining(struct margin_lanes_data arg)
101 char *ind_dirs[] = { "Up", "Down", "Left", "Right" };
102 char *non_ind_dirs[] = { "Voltage", "", "Timing" };
104 if (arg.verbosity > 0)
106 margin_log("\033[2K\rMargining - ");
108 margin_log("%s", ind_dirs[arg.dir]);
110 margin_log("%s", non_ind_dirs[arg.dir]);
112 u8 lanes_counter = 0;
113 margin_log(" - Lanes ");
114 margin_log("[%d", arg.lanes_numbers[0]);
115 for (int i = 1; i < arg.lanes_n; i++)
117 if (arg.lanes_numbers[i] - 1 == arg.lanes_numbers[i - 1])
120 if (lanes_counter == 1)
122 if (i + 1 == arg.lanes_n)
123 margin_log("%d", arg.lanes_numbers[i]);
127 if (lanes_counter > 0)
128 margin_log("%d", arg.lanes_numbers[i - 1]);
129 margin_log(",%d", arg.lanes_numbers[i]);
135 u64 lane_eta_s = (arg.steps_lane_total - arg.steps_lane_done) * MARGIN_STEP_MS / 1000;
136 u64 total_eta_s = *arg.steps_utility * MARGIN_STEP_MS / 1000 + lane_eta_s;
137 margin_log(" - ETA: %3ds Steps: %3d Total ETA: %3dm %2ds", lane_eta_s, arg.steps_lane_done,
138 total_eta_s / 60, total_eta_s % 60);
145 margin_log_hw_quirks(struct margin_recv *recv)
147 switch (recv->dev->hw)
149 case MARGIN_ICE_LAKE_RC:
150 if (recv->recvn == 1)
151 margin_log("\nRx(A) is Intel Ice Lake RC port.\n"
152 "Applying next quirks for margining process:\n"
153 " - Set MaxVoltageOffset to 12 (120 mV).\n");