2 * The PCI Library -- Direct Configuration access via i386 Ports
4 * Copyright (c) 1997--2003 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL.
19 static int intel_iopl_set = -1;
24 if (intel_iopl_set < 0)
25 intel_iopl_set = (iopl(3) < 0) ? 0 : 1;
26 return intel_iopl_set;
30 conf12_init(struct pci_access *a)
32 if (!intel_setup_io())
33 a->error("You need to be root to have access to I/O ports.");
37 conf12_cleanup(struct pci_access *a UNUSED)
44 * Before we decide to use direct hardware access mechanisms, we try to do some
45 * trivial checks to ensure it at least _seems_ to be working -- we just test
46 * whether bus 00 contains a host bridge (this is similar to checking
47 * techniques used in XFree86, but ours should be more reliable since we
48 * attempt to make use of direct access hints provided by the PCI BIOS).
50 * This should be close to trivial, but it isn't, because there are buggy
51 * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
55 intel_sanity_check(struct pci_access *a, struct pci_methods *m)
59 a->debug("...sanity check");
62 for(d.dev = 0; d.dev < 32; d.dev++)
65 if (m->read(&d, PCI_CLASS_DEVICE, (byte *) &class, sizeof(class)) &&
66 (class == cpu_to_le16(PCI_CLASS_BRIDGE_HOST) || class == cpu_to_le16(PCI_CLASS_DISPLAY_VGA)) ||
67 m->read(&d, PCI_VENDOR_ID, (byte *) &vendor, sizeof(vendor)) &&
68 (vendor == cpu_to_le16(PCI_VENDOR_ID_INTEL) || vendor == cpu_to_le16(PCI_VENDOR_ID_COMPAQ)))
70 a->debug("...outside the Asylum at 0/%02x/0", d.dev);
74 a->debug("...insane");
79 * Configuration type 1
82 #define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (bus << 16) | (device_fn << 8) | (where & ~3))
85 conf1_detect(struct pci_access *a)
90 if (!intel_setup_io())
92 a->debug("...no I/O permission");
97 outl (0x80000000, 0xCF8);
98 if (inl (0xCF8) == 0x80000000)
102 res = intel_sanity_check(a, &pm_intel_conf1);
107 conf1_read(struct pci_dev *d, int pos, byte *buf, int len)
109 int addr = 0xcfc + (pos&3);
110 outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
118 ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
121 ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
124 return pci_generic_block_read(d, pos, buf, len);
130 conf1_write(struct pci_dev *d, int pos, byte *buf, int len)
132 int addr = 0xcfc + (pos&3);
133 outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
141 outw(le16_to_cpu(((u16 *) buf)[0]), addr);
144 outl(le32_to_cpu(((u32 *) buf)[0]), addr);
147 return pci_generic_block_write(d, pos, buf, len);
153 * Configuration type 2. Obsolete and brain-damaged, but existing.
157 conf2_detect(struct pci_access *a)
159 if (!intel_setup_io())
161 a->debug("...no I/O permission");
165 /* This is ugly and tends to produce false positives. Beware. */
170 if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00)
171 return intel_sanity_check(a, &pm_intel_conf2);
177 conf2_read(struct pci_dev *d, int pos, byte *buf, int len)
179 int addr = 0xc000 | (d->dev << 8) | pos;
182 /* conf2 supports only 16 devices per bus */
184 outb((d->func << 1) | 0xf0, 0xcf8);
192 ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
195 ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
199 return pci_generic_block_read(d, pos, buf, len);
206 conf2_write(struct pci_dev *d, int pos, byte *buf, int len)
208 int addr = 0xc000 | (d->dev << 8) | pos;
211 d->access->error("conf2_write: only first 16 devices exist.");
212 outb((d->func << 1) | 0xf0, 0xcf8);
220 outw(le16_to_cpu(* (u16 *) buf), addr);
223 outl(le32_to_cpu(* (u32 *) buf), addr);
227 return pci_generic_block_write(d, pos, buf, len);
233 struct pci_methods pm_intel_conf1 = {
240 pci_generic_fill_info,
244 NULL /* cleanup_dev */
247 struct pci_methods pm_intel_conf2 = {
254 pci_generic_fill_info,
258 NULL /* cleanup_dev */