2 * The PCI Library -- Direct Configuration access via i386 Ports
4 * Copyright (c) 1997--2003 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL.
20 static int intel_iopl_set = -1;
25 if (intel_iopl_set < 0)
26 intel_iopl_set = (iopl(3) < 0) ? 0 : 1;
27 return intel_iopl_set;
31 intel_cleanup_io(void)
33 if (intel_iopl_set > 0)
40 /* The GNU Hurd doesn't have an iopl() call */
49 intel_cleanup_io(void)
55 conf12_init(struct pci_access *a)
57 if (!intel_setup_io())
58 a->error("You need to be root to have access to I/O ports.");
62 conf12_cleanup(struct pci_access *a UNUSED)
68 * Before we decide to use direct hardware access mechanisms, we try to do some
69 * trivial checks to ensure it at least _seems_ to be working -- we just test
70 * whether bus 00 contains a host bridge (this is similar to checking
71 * techniques used in XFree86, but ours should be more reliable since we
72 * attempt to make use of direct access hints provided by the PCI BIOS).
74 * This should be close to trivial, but it isn't, because there are buggy
75 * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
79 intel_sanity_check(struct pci_access *a, struct pci_methods *m)
83 a->debug("...sanity check");
86 for(d.dev = 0; d.dev < 32; d.dev++)
89 if (m->read(&d, PCI_CLASS_DEVICE, (byte *) &class, sizeof(class)) &&
90 (class == cpu_to_le16(PCI_CLASS_BRIDGE_HOST) || class == cpu_to_le16(PCI_CLASS_DISPLAY_VGA)) ||
91 m->read(&d, PCI_VENDOR_ID, (byte *) &vendor, sizeof(vendor)) &&
92 (vendor == cpu_to_le16(PCI_VENDOR_ID_INTEL) || vendor == cpu_to_le16(PCI_VENDOR_ID_COMPAQ)))
94 a->debug("...outside the Asylum at 0/%02x/0", d.dev);
98 a->debug("...insane");
103 * Configuration type 1
106 #define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (bus << 16) | (device_fn << 8) | (where & ~3))
109 conf1_detect(struct pci_access *a)
114 if (!intel_setup_io())
116 a->debug("...no I/O permission");
121 outl (0x80000000, 0xCF8);
122 if (inl (0xCF8) == 0x80000000)
126 res = intel_sanity_check(a, &pm_intel_conf1);
131 conf1_read(struct pci_dev *d, int pos, byte *buf, int len)
133 int addr = 0xcfc + (pos&3);
134 outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
142 ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
145 ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
148 return pci_generic_block_read(d, pos, buf, len);
154 conf1_write(struct pci_dev *d, int pos, byte *buf, int len)
156 int addr = 0xcfc + (pos&3);
157 outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
165 outw(le16_to_cpu(((u16 *) buf)[0]), addr);
168 outl(le32_to_cpu(((u32 *) buf)[0]), addr);
171 return pci_generic_block_write(d, pos, buf, len);
177 * Configuration type 2. Obsolete and brain-damaged, but existing.
181 conf2_detect(struct pci_access *a)
183 if (!intel_setup_io())
185 a->debug("...no I/O permission");
189 /* This is ugly and tends to produce false positives. Beware. */
194 if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00)
195 return intel_sanity_check(a, &pm_intel_conf2);
201 conf2_read(struct pci_dev *d, int pos, byte *buf, int len)
203 int addr = 0xc000 | (d->dev << 8) | pos;
206 /* conf2 supports only 16 devices per bus */
208 outb((d->func << 1) | 0xf0, 0xcf8);
216 ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
219 ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
223 return pci_generic_block_read(d, pos, buf, len);
230 conf2_write(struct pci_dev *d, int pos, byte *buf, int len)
232 int addr = 0xc000 | (d->dev << 8) | pos;
235 d->access->error("conf2_write: only first 16 devices exist.");
236 outb((d->func << 1) | 0xf0, 0xcf8);
244 outw(le16_to_cpu(* (u16 *) buf), addr);
247 outl(le32_to_cpu(* (u32 *) buf), addr);
251 return pci_generic_block_write(d, pos, buf, len);
257 struct pci_methods pm_intel_conf1 = {
264 pci_generic_fill_info,
268 NULL /* cleanup_dev */
271 struct pci_methods pm_intel_conf2 = {
278 pci_generic_fill_info,
282 NULL /* cleanup_dev */