2 * The PCI Library -- Direct Configuration access via i386 Ports
4 * Copyright (c) 1997--2004 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL.
14 #include "i386-io-linux.h"
16 #include "i386-io-hurd.h"
17 #elif defined(OS_SUNOS)
18 #include "i386-io-sunos.h"
19 #elif defined(OS_WINDOWS)
20 #include "i386-io-windows.h"
22 #error Do not know how to access I/O ports on this OS.
26 conf12_init(struct pci_access *a)
28 if (!intel_setup_io())
29 a->error("You need to be root to have access to I/O ports.");
33 conf12_cleanup(struct pci_access *a UNUSED)
39 * Before we decide to use direct hardware access mechanisms, we try to do some
40 * trivial checks to ensure it at least _seems_ to be working -- we just test
41 * whether bus 00 contains a host bridge (this is similar to checking
42 * techniques used in XFree86, but ours should be more reliable since we
43 * attempt to make use of direct access hints provided by the PCI BIOS).
45 * This should be close to trivial, but it isn't, because there are buggy
46 * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
50 intel_sanity_check(struct pci_access *a, struct pci_methods *m)
54 a->debug("...sanity check");
57 for(d.dev = 0; d.dev < 32; d.dev++)
60 if (m->read(&d, PCI_CLASS_DEVICE, (byte *) &class, sizeof(class)) &&
61 (class == cpu_to_le16(PCI_CLASS_BRIDGE_HOST) || class == cpu_to_le16(PCI_CLASS_DISPLAY_VGA)) ||
62 m->read(&d, PCI_VENDOR_ID, (byte *) &vendor, sizeof(vendor)) &&
63 (vendor == cpu_to_le16(PCI_VENDOR_ID_INTEL) || vendor == cpu_to_le16(PCI_VENDOR_ID_COMPAQ)))
65 a->debug("...outside the Asylum at 0/%02x/0", d.dev);
69 a->debug("...insane");
74 * Configuration type 1
77 #define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (bus << 16) | (device_fn << 8) | (where & ~3))
80 conf1_detect(struct pci_access *a)
85 if (!intel_setup_io())
87 a->debug("...no I/O permission");
92 outl (0x80000000, 0xCF8);
93 if (inl (0xCF8) == 0x80000000)
97 res = intel_sanity_check(a, &pm_intel_conf1);
102 conf1_read(struct pci_dev *d, int pos, byte *buf, int len)
104 int addr = 0xcfc + (pos&3);
109 outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
117 ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
120 ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
123 return pci_generic_block_read(d, pos, buf, len);
129 conf1_write(struct pci_dev *d, int pos, byte *buf, int len)
131 int addr = 0xcfc + (pos&3);
136 outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
144 outw(le16_to_cpu(((u16 *) buf)[0]), addr);
147 outl(le32_to_cpu(((u32 *) buf)[0]), addr);
150 return pci_generic_block_write(d, pos, buf, len);
156 * Configuration type 2. Obsolete and brain-damaged, but existing.
160 conf2_detect(struct pci_access *a)
162 if (!intel_setup_io())
164 a->debug("...no I/O permission");
168 /* This is ugly and tends to produce false positives. Beware. */
173 if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00)
174 return intel_sanity_check(a, &pm_intel_conf2);
180 conf2_read(struct pci_dev *d, int pos, byte *buf, int len)
182 int addr = 0xc000 | (d->dev << 8) | pos;
188 /* conf2 supports only 16 devices per bus */
190 outb((d->func << 1) | 0xf0, 0xcf8);
198 ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
201 ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
205 return pci_generic_block_read(d, pos, buf, len);
212 conf2_write(struct pci_dev *d, int pos, byte *buf, int len)
214 int addr = 0xc000 | (d->dev << 8) | pos;
220 d->access->error("conf2_write: only first 16 devices exist.");
221 outb((d->func << 1) | 0xf0, 0xcf8);
229 outw(le16_to_cpu(* (u16 *) buf), addr);
232 outl(le32_to_cpu(* (u32 *) buf), addr);
236 return pci_generic_block_write(d, pos, buf, len);
242 struct pci_methods pm_intel_conf1 = {
249 pci_generic_fill_info,
253 NULL /* cleanup_dev */
256 struct pci_methods pm_intel_conf2 = {
263 pci_generic_fill_info,
267 NULL /* cleanup_dev */