2 * The PCI Library -- Direct Configuration access via i386 Ports
4 * Copyright (c) 1997--2003 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL.
14 #include "i386-io-linux.h"
16 #include "i386-io-hurd.h"
17 #elif defined(OS_SunOS)
18 #include "i386-io-sunos.h"
20 #error Do not know how to access I/O ports on this OS.
24 conf12_init(struct pci_access *a)
26 if (!intel_setup_io())
27 a->error("You need to be root to have access to I/O ports.");
31 conf12_cleanup(struct pci_access *a UNUSED)
37 * Before we decide to use direct hardware access mechanisms, we try to do some
38 * trivial checks to ensure it at least _seems_ to be working -- we just test
39 * whether bus 00 contains a host bridge (this is similar to checking
40 * techniques used in XFree86, but ours should be more reliable since we
41 * attempt to make use of direct access hints provided by the PCI BIOS).
43 * This should be close to trivial, but it isn't, because there are buggy
44 * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
48 intel_sanity_check(struct pci_access *a, struct pci_methods *m)
52 a->debug("...sanity check");
55 for(d.dev = 0; d.dev < 32; d.dev++)
58 if (m->read(&d, PCI_CLASS_DEVICE, (byte *) &class, sizeof(class)) &&
59 (class == cpu_to_le16(PCI_CLASS_BRIDGE_HOST) || class == cpu_to_le16(PCI_CLASS_DISPLAY_VGA)) ||
60 m->read(&d, PCI_VENDOR_ID, (byte *) &vendor, sizeof(vendor)) &&
61 (vendor == cpu_to_le16(PCI_VENDOR_ID_INTEL) || vendor == cpu_to_le16(PCI_VENDOR_ID_COMPAQ)))
63 a->debug("...outside the Asylum at 0/%02x/0", d.dev);
67 a->debug("...insane");
72 * Configuration type 1
75 #define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (bus << 16) | (device_fn << 8) | (where & ~3))
78 conf1_detect(struct pci_access *a)
83 if (!intel_setup_io())
85 a->debug("...no I/O permission");
90 outl (0x80000000, 0xCF8);
91 if (inl (0xCF8) == 0x80000000)
95 res = intel_sanity_check(a, &pm_intel_conf1);
100 conf1_read(struct pci_dev *d, int pos, byte *buf, int len)
102 int addr = 0xcfc + (pos&3);
103 outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
111 ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
114 ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
117 return pci_generic_block_read(d, pos, buf, len);
123 conf1_write(struct pci_dev *d, int pos, byte *buf, int len)
125 int addr = 0xcfc + (pos&3);
126 outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
134 outw(le16_to_cpu(((u16 *) buf)[0]), addr);
137 outl(le32_to_cpu(((u32 *) buf)[0]), addr);
140 return pci_generic_block_write(d, pos, buf, len);
146 * Configuration type 2. Obsolete and brain-damaged, but existing.
150 conf2_detect(struct pci_access *a)
152 if (!intel_setup_io())
154 a->debug("...no I/O permission");
158 /* This is ugly and tends to produce false positives. Beware. */
163 if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00)
164 return intel_sanity_check(a, &pm_intel_conf2);
170 conf2_read(struct pci_dev *d, int pos, byte *buf, int len)
172 int addr = 0xc000 | (d->dev << 8) | pos;
175 /* conf2 supports only 16 devices per bus */
177 outb((d->func << 1) | 0xf0, 0xcf8);
185 ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
188 ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
192 return pci_generic_block_read(d, pos, buf, len);
199 conf2_write(struct pci_dev *d, int pos, byte *buf, int len)
201 int addr = 0xc000 | (d->dev << 8) | pos;
204 d->access->error("conf2_write: only first 16 devices exist.");
205 outb((d->func << 1) | 0xf0, 0xcf8);
213 outw(le16_to_cpu(* (u16 *) buf), addr);
216 outl(le32_to_cpu(* (u32 *) buf), addr);
220 return pci_generic_block_write(d, pos, buf, len);
226 struct pci_methods pm_intel_conf1 = {
233 pci_generic_fill_info,
237 NULL /* cleanup_dev */
240 struct pci_methods pm_intel_conf2 = {
247 pci_generic_fill_info,
251 NULL /* cleanup_dev */