2 * $Id: i386-ports.c,v 1.2 2000/01/24 15:36:09 mj Exp $
4 * The PCI Library -- Direct Configuration access via i386 Ports
6 * Copyright (c) 1997--1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
8 * Can be freely distributed and used under the terms of the GNU GPL.
21 static int intel_iopl_set = -1;
26 if (intel_iopl_set < 0)
27 intel_iopl_set = (iopl(3) < 0) ? 0 : 1;
28 return intel_iopl_set;
32 conf12_init(struct pci_access *a)
34 if (!intel_setup_io())
35 a->error("You need to be root to have access to I/O ports.");
39 conf12_cleanup(struct pci_access * UNUSED a)
46 * Before we decide to use direct hardware access mechanisms, we try to do some
47 * trivial checks to ensure it at least _seems_ to be working -- we just test
48 * whether bus 00 contains a host bridge (this is similar to checking
49 * techniques used in XFree86, but ours should be more reliable since we
50 * attempt to make use of direct access hints provided by the PCI BIOS).
52 * This should be close to trivial, but it isn't, because there are buggy
53 * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
57 intel_sanity_check(struct pci_access *a, struct pci_methods *m)
61 a->debug("...sanity check");
64 for(d.dev = 0; d.dev < 32; d.dev++)
67 if (m->read(&d, PCI_CLASS_DEVICE, (byte *) &class, sizeof(class)) &&
68 (class == cpu_to_le16(PCI_CLASS_BRIDGE_HOST) || class == cpu_to_le16(PCI_CLASS_DISPLAY_VGA)) ||
69 m->read(&d, PCI_VENDOR_ID, (byte *) &vendor, sizeof(vendor)) &&
70 (vendor == cpu_to_le16(PCI_VENDOR_ID_INTEL) || vendor == cpu_to_le16(PCI_VENDOR_ID_COMPAQ)))
72 a->debug("...outside the Asylum at 0/%02x/0", d.dev);
76 a->debug("...insane");
81 * Configuration type 1
84 #define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (bus << 16) | (device_fn << 8) | (where & ~3))
87 conf1_detect(struct pci_access *a)
92 if (!intel_setup_io())
94 a->debug("...no I/O permission");
99 outl (0x80000000, 0xCF8);
100 if (inl (0xCF8) == 0x80000000)
104 res = intel_sanity_check(a, &pm_intel_conf1);
109 conf1_read(struct pci_dev *d, int pos, byte *buf, int len)
111 int addr = 0xcfc + (pos&3);
112 outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
120 ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
123 ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
126 return pci_generic_block_read(d, pos, buf, len);
132 conf1_write(struct pci_dev *d, int pos, byte *buf, int len)
134 int addr = 0xcfc + (pos&3);
135 outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
143 outw(le16_to_cpu(((u16 *) buf)[0]), addr);
146 outl(le32_to_cpu(((u32 *) buf)[0]), addr);
149 return pci_generic_block_write(d, pos, buf, len);
155 * Configuration type 2. Obsolete and brain-damaged, but existing.
159 conf2_detect(struct pci_access *a)
161 if (!intel_setup_io())
163 a->debug("...no I/O permission");
167 /* This is ugly and tends to produce false positives. Beware. */
172 if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00)
173 return intel_sanity_check(a, &pm_intel_conf2);
179 conf2_read(struct pci_dev *d, int pos, byte *buf, int len)
181 int addr = 0xc000 | (d->dev << 8) | pos;
184 /* conf2 supports only 16 devices per bus */
186 outb((d->func << 1) | 0xf0, 0xcf8);
194 ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
197 ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
201 return pci_generic_block_read(d, pos, buf, len);
208 conf2_write(struct pci_dev *d, int pos, byte *buf, int len)
210 int addr = 0xc000 | (d->dev << 8) | pos;
213 d->access->error("conf2_write: only first 16 devices exist.");
214 outb((d->func << 1) | 0xf0, 0xcf8);
222 outw(le16_to_cpu(* (u16 *) buf), addr);
225 outl(le32_to_cpu(* (u32 *) buf), addr);
229 return pci_generic_block_write(d, pos, buf, len);
235 struct pci_methods pm_intel_conf1 = {
242 pci_generic_fill_info,
246 NULL /* cleanup_dev */
249 struct pci_methods pm_intel_conf2 = {
256 pci_generic_fill_info,
260 NULL /* cleanup_dev */