2 * The PCI Library -- Direct Configuration access via i386 Ports
4 * Copyright (c) 1997--2006 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL.
15 #if defined(PCI_OS_LINUX)
16 #include "i386-io-linux.h"
17 #elif defined(PCI_OS_GNU)
18 #include "i386-io-hurd.h"
19 #elif defined(PCI_OS_SUNOS)
20 #include "i386-io-sunos.h"
21 #elif defined(PCI_OS_WINDOWS)
22 #include "i386-io-windows.h"
24 #error Do not know how to access I/O ports on this OS.
28 conf12_init(struct pci_access *a)
30 if (!intel_setup_io())
31 a->error("You need to be root to have access to I/O ports.");
35 conf12_cleanup(struct pci_access *a UNUSED)
41 * Before we decide to use direct hardware access mechanisms, we try to do some
42 * trivial checks to ensure it at least _seems_ to be working -- we just test
43 * whether bus 00 contains a host bridge (this is similar to checking
44 * techniques used in XFree86, but ours should be more reliable since we
45 * attempt to make use of direct access hints provided by the PCI BIOS).
47 * This should be close to trivial, but it isn't, because there are buggy
48 * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
52 intel_sanity_check(struct pci_access *a, struct pci_methods *m)
56 a->debug("...sanity check");
59 for(d.dev = 0; d.dev < 32; d.dev++)
62 if (m->read(&d, PCI_CLASS_DEVICE, (byte *) &class, sizeof(class)) &&
63 (class == cpu_to_le16(PCI_CLASS_BRIDGE_HOST) || class == cpu_to_le16(PCI_CLASS_DISPLAY_VGA)) ||
64 m->read(&d, PCI_VENDOR_ID, (byte *) &vendor, sizeof(vendor)) &&
65 (vendor == cpu_to_le16(PCI_VENDOR_ID_INTEL) || vendor == cpu_to_le16(PCI_VENDOR_ID_COMPAQ)))
67 a->debug("...outside the Asylum at 0/%02x/0", d.dev);
71 a->debug("...insane");
76 * Configuration type 1
79 #define CONFIG_CMD(bus, device_fn, where) (0x80000000 | (bus << 16) | (device_fn << 8) | (where & ~3))
82 conf1_detect(struct pci_access *a)
87 if (!intel_setup_io())
89 a->debug("...no I/O permission");
94 outl (0x80000000, 0xCF8);
95 if (inl (0xCF8) == 0x80000000)
99 res = intel_sanity_check(a, &pm_intel_conf1);
104 conf1_read(struct pci_dev *d, int pos, byte *buf, int len)
106 int addr = 0xcfc + (pos&3);
111 outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
119 ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
122 ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
125 return pci_generic_block_read(d, pos, buf, len);
131 conf1_write(struct pci_dev *d, int pos, byte *buf, int len)
133 int addr = 0xcfc + (pos&3);
138 outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
146 outw(le16_to_cpu(((u16 *) buf)[0]), addr);
149 outl(le32_to_cpu(((u32 *) buf)[0]), addr);
152 return pci_generic_block_write(d, pos, buf, len);
158 * Configuration type 2. Obsolete and brain-damaged, but existing.
162 conf2_detect(struct pci_access *a)
164 if (!intel_setup_io())
166 a->debug("...no I/O permission");
170 /* This is ugly and tends to produce false positives. Beware. */
175 if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00)
176 return intel_sanity_check(a, &pm_intel_conf2);
182 conf2_read(struct pci_dev *d, int pos, byte *buf, int len)
184 int addr = 0xc000 | (d->dev << 8) | pos;
190 /* conf2 supports only 16 devices per bus */
192 outb((d->func << 1) | 0xf0, 0xcf8);
200 ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
203 ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
207 return pci_generic_block_read(d, pos, buf, len);
214 conf2_write(struct pci_dev *d, int pos, byte *buf, int len)
216 int addr = 0xc000 | (d->dev << 8) | pos;
222 d->access->error("conf2_write: only first 16 devices exist.");
223 outb((d->func << 1) | 0xf0, 0xcf8);
231 outw(le16_to_cpu(* (u16 *) buf), addr);
234 outl(le32_to_cpu(* (u32 *) buf), addr);
238 return pci_generic_block_write(d, pos, buf, len);
244 struct pci_methods pm_intel_conf1 = {
251 pci_generic_fill_info,
255 NULL /* cleanup_dev */
258 struct pci_methods pm_intel_conf2 = {
265 pci_generic_fill_info,
269 NULL /* cleanup_dev */