2 * The PCI Library -- PCI Header Structure (based on <linux/pci.h>)
4 * Copyright (c) 1997--2010 Martin Mares <mj@ucw.cz>
6 * Can be freely distributed and used under the terms of the GNU GPL v2+
8 * SPDX-License-Identifier: GPL-2.0-or-later
12 * Under PCI, each device has 256 bytes of configuration address space,
13 * of which the first 64 bytes are standardized as follows:
15 #define PCI_VENDOR_ID 0x00 /* 16 bits */
16 #define PCI_DEVICE_ID 0x02 /* 16 bits */
17 #define PCI_COMMAND 0x04 /* 16 bits */
18 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
19 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
20 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
21 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
22 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
23 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
24 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
25 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
26 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
27 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
28 #define PCI_COMMAND_DISABLE_INTx 0x400 /* PCIE: Disable INTx interrupts */
30 #define PCI_STATUS 0x06 /* 16 bits */
31 #define PCI_STATUS_INTx 0x08 /* PCIE: INTx interrupt pending */
32 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
33 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
34 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
35 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
36 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
37 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
38 #define PCI_STATUS_DEVSEL_FAST 0x000
39 #define PCI_STATUS_DEVSEL_MEDIUM 0x200
40 #define PCI_STATUS_DEVSEL_SLOW 0x400
41 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
42 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
43 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
44 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
45 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
47 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
49 #define PCI_REVISION_ID 0x08 /* Revision ID */
50 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
51 #define PCI_CLASS_DEVICE 0x0a /* Device class */
53 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
54 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
55 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
56 #define PCI_HEADER_TYPE_NORMAL 0
57 #define PCI_HEADER_TYPE_BRIDGE 1
58 #define PCI_HEADER_TYPE_CARDBUS 2
60 #define PCI_BIST 0x0f /* 8 bits */
61 #define PCI_BIST_CODE_MASK 0x0f /* Return result */
62 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
63 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
66 * Base addresses specify locations in memory or I/O space.
67 * Decoded size can be determined by writing a value of
68 * 0xffffffff to the register, and reading it back. Only
71 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
72 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
73 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
74 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
75 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
76 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
77 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
78 #define PCI_BASE_ADDRESS_SPACE_IO 0x01
79 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
80 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
81 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
82 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
83 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
84 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
85 #define PCI_BASE_ADDRESS_MEM_MASK (~(pciaddr_t)0x0f)
86 #define PCI_BASE_ADDRESS_IO_MASK (~(pciaddr_t)0x03)
87 /* bit 1 is reserved if address_space = 1 */
89 /* Header type 0 (normal devices) */
90 #define PCI_CARDBUS_CIS 0x28
91 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
92 #define PCI_SUBSYSTEM_ID 0x2e
93 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
94 #define PCI_ROM_ADDRESS_ENABLE 0x01
95 #define PCI_ROM_ADDRESS_MASK (~(pciaddr_t)0x7ff)
97 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
99 /* 0x35-0x3b are reserved */
100 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
101 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
102 #define PCI_MIN_GNT 0x3e /* 8 bits */
103 #define PCI_MAX_LAT 0x3f /* 8 bits */
105 /* Header type 1 (PCI-to-PCI bridges) */
106 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
107 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
108 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
109 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
110 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
111 #define PCI_IO_LIMIT 0x1d
112 #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
113 #define PCI_IO_RANGE_TYPE_16 0x00
114 #define PCI_IO_RANGE_TYPE_32 0x01
115 #define PCI_IO_RANGE_MASK ~0x0f
116 #define PCI_SEC_STATUS 0x1e /* Secondary status register */
117 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */
118 #define PCI_MEMORY_LIMIT 0x22
119 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
120 #define PCI_MEMORY_RANGE_MASK ~0x0f
121 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
122 #define PCI_PREF_MEMORY_LIMIT 0x26
123 #define PCI_PREF_RANGE_TYPE_MASK 0x0f
124 #define PCI_PREF_RANGE_TYPE_32 0x00
125 #define PCI_PREF_RANGE_TYPE_64 0x01
126 #define PCI_PREF_RANGE_MASK ~0x0f
127 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
128 #define PCI_PREF_LIMIT_UPPER32 0x2c
129 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
130 #define PCI_IO_LIMIT_UPPER16 0x32
131 /* 0x34 same as for htype 0 */
132 /* 0x35-0x3b is reserved */
133 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
134 /* 0x3c-0x3d are same as for htype 0 */
135 #define PCI_BRIDGE_CONTROL 0x3e
136 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
137 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
138 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
139 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
140 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
141 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
142 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
143 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
144 #define PCI_BRIDGE_CTL_PRI_DISCARD_TIMER 0x100 /* PCI-X? */
145 #define PCI_BRIDGE_CTL_SEC_DISCARD_TIMER 0x200 /* PCI-X? */
146 #define PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS 0x400 /* PCI-X? */
147 #define PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN 0x800 /* PCI-X? */
149 /* Header type 2 (CardBus bridges) */
150 #define PCI_CB_CAPABILITY_LIST 0x14
152 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
153 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
154 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
155 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
156 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
157 #define PCI_CB_MEMORY_BASE_0 0x1c
158 #define PCI_CB_MEMORY_LIMIT_0 0x20
159 #define PCI_CB_MEMORY_BASE_1 0x24
160 #define PCI_CB_MEMORY_LIMIT_1 0x28
161 #define PCI_CB_IO_BASE_0 0x2c
162 #define PCI_CB_IO_BASE_0_HI 0x2e
163 #define PCI_CB_IO_LIMIT_0 0x30
164 #define PCI_CB_IO_LIMIT_0_HI 0x32
165 #define PCI_CB_IO_BASE_1 0x34
166 #define PCI_CB_IO_BASE_1_HI 0x36
167 #define PCI_CB_IO_LIMIT_1 0x38
168 #define PCI_CB_IO_LIMIT_1_HI 0x3a
169 #define PCI_CB_IO_RANGE_MASK ~0x03
170 /* 0x3c-0x3d are same as for htype 0 */
171 #define PCI_CB_BRIDGE_CONTROL 0x3e
172 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
173 #define PCI_CB_BRIDGE_CTL_SERR 0x02
174 #define PCI_CB_BRIDGE_CTL_ISA 0x04
175 #define PCI_CB_BRIDGE_CTL_VGA 0x08
176 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
177 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
178 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
179 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
180 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
181 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
182 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
183 #define PCI_CB_SUBSYSTEM_ID 0x42
184 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
185 /* 0x48-0x7f reserved */
187 /* Capability lists */
189 #define PCI_CAP_LIST_ID 0 /* Capability ID */
190 #define PCI_CAP_ID_NULL 0x00 /* Null Capability */
191 #define PCI_CAP_ID_PM 0x01 /* Power Management */
192 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
193 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
194 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
195 #define PCI_CAP_ID_MSI 0x05 /* Message Signaled Interrupts */
196 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
197 #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
198 #define PCI_CAP_ID_HT 0x08 /* HyperTransport */
199 #define PCI_CAP_ID_VNDR 0x09 /* Vendor specific */
200 #define PCI_CAP_ID_DBG 0x0A /* Debug port */
201 #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
202 #define PCI_CAP_ID_HOTPLUG 0x0C /* PCI hot-plug */
203 #define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
204 #define PCI_CAP_ID_AGP3 0x0E /* AGP 8x */
205 #define PCI_CAP_ID_SECURE 0x0F /* Secure device (?) */
206 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
207 #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
208 #define PCI_CAP_ID_SATA 0x12 /* Serial-ATA HBA */
209 #define PCI_CAP_ID_AF 0x13 /* Advanced features of PCI devices integrated in PCIe root cplx */
210 #define PCI_CAP_ID_EA 0x14 /* Enhanced Allocation */
211 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
212 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
213 #define PCI_CAP_SIZEOF 4
215 /* Capabilities residing in the PCI Express extended configuration space */
217 #define PCI_EXT_CAP_ID_NULL 0x00 /* Null Capability */
218 #define PCI_EXT_CAP_ID_AER 0x01 /* Advanced Error Reporting */
219 #define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel */
220 #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
221 #define PCI_EXT_CAP_ID_PB 0x04 /* Power Budgeting */
222 #define PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */
223 #define PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declaration */
224 #define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */
225 #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */
226 #define PCI_EXT_CAP_ID_VC2 0x09 /* Virtual Channel (2nd ID) */
227 #define PCI_EXT_CAP_ID_RCRB 0x0a /* Root Complex Register Block */
228 #define PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */
229 #define PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */
230 #define PCI_EXT_CAP_ID_ARI 0x0e /* Alternative Routing-ID Interpretation */
231 #define PCI_EXT_CAP_ID_ATS 0x0f /* Address Translation Service */
232 #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */
233 #define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi-Root I/O Virtualization */
234 #define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */
235 #define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */
236 #define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */
237 #define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */
238 #define PCI_EXT_CAP_ID_TPH 0x17 /* Transaction processing hints */
239 #define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */
240 #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCI Express */
241 #define PCI_EXT_CAP_ID_PMUX 0x1a /* Protocol Multiplexing */
242 #define PCI_EXT_CAP_ID_PASID 0x1b /* Process Address Space ID */
243 #define PCI_EXT_CAP_ID_LNR 0x1c /* LN Requester */
244 #define PCI_EXT_CAP_ID_DPC 0x1d /* Downstream Port Containment */
245 #define PCI_EXT_CAP_ID_L1PM 0x1e /* L1 PM Substates */
246 #define PCI_EXT_CAP_ID_PTM 0x1f /* Precision Time Measurement */
247 #define PCI_EXT_CAP_ID_M_PCIE 0x20 /* PCIe over M-PHY */
248 #define PCI_EXT_CAP_ID_FRS 0x21 /* FRS Queuing */
249 #define PCI_EXT_CAP_ID_RTR 0x22 /* Readiness Time Reporting */
250 #define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */
251 #define PCI_EXT_CAP_ID_VF_REBAR 0x24 /* VF Resizable BAR */
252 #define PCI_EXT_CAP_ID_DLNK 0x25 /* Data Link Feature */
253 #define PCI_EXT_CAP_ID_16GT 0x26 /* Physical Layer 16.0 GT/s */
254 #define PCI_EXT_CAP_ID_LMR 0x27 /* Lane Margining at Receiver */
255 #define PCI_EXT_CAP_ID_HIER_ID 0x28 /* Hierarchy ID */
256 #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */
257 #define PCI_EXT_CAP_ID_32GT 0x2a /* Physical Layer 32.0 GT/s */
258 #define PCI_EXT_CAP_ID_DOE 0x2e /* Data Object Exchange */
260 /*** Definitions of capabilities ***/
262 /* Power Management Registers */
264 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version (2=PM1.1) */
265 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* Clock required for PME generation */
266 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization required */
267 #define PCI_PM_CAP_AUX_C_MASK 0x01c0 /* Maximum aux current required in D3cold */
268 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
269 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
270 #define PCI_PM_CAP_PME_D0 0x0800 /* PME can be asserted from D0 */
271 #define PCI_PM_CAP_PME_D1 0x1000 /* PME can be asserted from D1 */
272 #define PCI_PM_CAP_PME_D2 0x2000 /* PME can be asserted from D2 */
273 #define PCI_PM_CAP_PME_D3_HOT 0x4000 /* PME can be asserted from D3hot */
274 #define PCI_PM_CAP_PME_D3_COLD 0x8000 /* PME can be asserted from D3cold */
275 #define PCI_PM_CTRL 4 /* PM control and status register */
276 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
277 #define PCI_PM_CTRL_NO_SOFT_RST 0x0008 /* No Soft Reset from D3hot to D0 */
278 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
279 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* PM table data index */
280 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* PM table data scaling factor */
281 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
282 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions */
283 #define PCI_PM_PPB_B2_B3 0x40 /* If bridge enters D3hot, bus enters: 0=B3, 1=B2 */
284 #define PCI_PM_BPCC_ENABLE 0x80 /* Secondary bus is power managed */
285 #define PCI_PM_DATA_REGISTER 7 /* PM table contents read here */
286 #define PCI_PM_SIZEOF 8
290 #define PCI_AGP_VERSION 2 /* BCD version number */
291 #define PCI_AGP_RFU 3 /* Rest of capability flags */
292 #define PCI_AGP_STATUS 4 /* Status register */
293 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
294 #define PCI_AGP_STATUS_ISOCH 0x10000 /* Isochronous transactions supported */
295 #define PCI_AGP_STATUS_ARQSZ_MASK 0xe000 /* log2(optimum async req size in bytes) - 4 */
296 #define PCI_AGP_STATUS_CAL_MASK 0x1c00 /* Calibration cycle timing */
297 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
298 #define PCI_AGP_STATUS_ITA_COH 0x0100 /* In-aperture accesses always coherent */
299 #define PCI_AGP_STATUS_GART64 0x0080 /* 64-bit GART entries supported */
300 #define PCI_AGP_STATUS_HTRANS 0x0040 /* If 0, core logic can xlate host CPU accesses thru aperture */
301 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing cycles supported */
302 #define PCI_AGP_STATUS_FW 0x0010 /* Fast write transfers supported */
303 #define PCI_AGP_STATUS_AGP3 0x0008 /* AGP3 mode supported */
304 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported (RFU in AGP3 mode) */
305 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported (8x in AGP3 mode) */
306 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported (4x in AGP3 mode) */
307 #define PCI_AGP_COMMAND 8 /* Control register */
308 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
309 #define PCI_AGP_COMMAND_ARQSZ_MASK 0xe000 /* log2(optimum async req size in bytes) - 4 */
310 #define PCI_AGP_COMMAND_CAL_MASK 0x1c00 /* Calibration cycle timing */
311 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
312 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
313 #define PCI_AGP_COMMAND_GART64 0x0080 /* 64-bit GART entries enabled */
314 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow generation of 64-bit addr cycles */
315 #define PCI_AGP_COMMAND_FW 0x0010 /* Enable FW transfers */
316 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate (RFU in AGP3 mode) */
317 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate (8x in AGP3 mode) */
318 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate (4x in AGP3 mode) */
319 #define PCI_AGP_SIZEOF 12
321 /* Vital Product Data */
323 #define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
324 #define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */
325 #define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
326 #define PCI_VPD_DATA 4 /* 32-bits of data returned here */
328 /* Slot Identification */
330 #define PCI_SID_ESR 2 /* Expansion Slot Register */
331 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
332 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
333 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
335 /* Message Signaled Interrupts registers */
337 #define PCI_MSI_FLAGS 2 /* Various flags */
338 #define PCI_MSI_FLAGS_MASK_BIT 0x100 /* interrupt masking & reporting supported */
339 #define PCI_MSI_FLAGS_64BIT 0x080 /* 64-bit addresses allowed */
340 #define PCI_MSI_FLAGS_QSIZE 0x070 /* Message queue size configured */
341 #define PCI_MSI_FLAGS_QMASK 0x00e /* Maximum queue size available */
342 #define PCI_MSI_FLAGS_ENABLE 0x001 /* MSI feature enabled */
343 #define PCI_MSI_RFU 3 /* Rest of capability flags */
344 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
345 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
346 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
347 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
348 #define PCI_MSI_MASK_BIT_32 12 /* per-vector masking for 32-bit devices */
349 #define PCI_MSI_MASK_BIT_64 16 /* per-vector masking for 64-bit devices */
350 #define PCI_MSI_PENDING_32 16 /* per-vector interrupt pending for 32-bit devices */
351 #define PCI_MSI_PENDING_64 20 /* per-vector interrupt pending for 64-bit devices */
354 #define PCI_PCIX_COMMAND 2 /* Command register offset */
355 #define PCI_PCIX_COMMAND_DPERE 0x0001 /* Data Parity Error Recover Enable */
356 #define PCI_PCIX_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */
357 #define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT 0x000c /* Maximum Memory Read Byte Count */
358 #define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS 0x0070
359 #define PCI_PCIX_COMMAND_RESERVED 0xf80
360 #define PCI_PCIX_STATUS 4 /* Status register offset */
361 #define PCI_PCIX_STATUS_FUNCTION 0x00000007
362 #define PCI_PCIX_STATUS_DEVICE 0x000000f8
363 #define PCI_PCIX_STATUS_BUS 0x0000ff00
364 #define PCI_PCIX_STATUS_64BIT 0x00010000
365 #define PCI_PCIX_STATUS_133MHZ 0x00020000
366 #define PCI_PCIX_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */
367 #define PCI_PCIX_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */
368 #define PCI_PCIX_STATUS_DEVICE_COMPLEXITY 0x00100000 /* 0 = simple device, 1 = bridge device */
369 #define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT 0x00600000 /* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */
370 #define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS 0x03800000
371 #define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE 0x1c000000
372 #define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS 0x20000000 /* Received Split Completion Error Message */
373 #define PCI_PCIX_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
374 #define PCI_PCIX_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
375 #define PCI_PCIX_SIZEOF 4
378 #define PCI_PCIX_BRIDGE_SEC_STATUS 2 /* Secondary bus status register offset */
379 #define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT 0x0001
380 #define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ 0x0002
381 #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED 0x0004 /* Split Completion Discarded on secondary bus */
382 #define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC 0x0008 /* Unexpected Split Completion on secondary bus */
383 #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN 0x0010 /* Split Completion Overrun on secondary bus */
384 #define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED 0x0020
385 #define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ 0x01c0
386 #define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED 0xfe00
387 #define PCI_PCIX_BRIDGE_STATUS 4 /* Primary bus status register offset */
388 #define PCI_PCIX_BRIDGE_STATUS_FUNCTION 0x00000007
389 #define PCI_PCIX_BRIDGE_STATUS_DEVICE 0x000000f8
390 #define PCI_PCIX_BRIDGE_STATUS_BUS 0x0000ff00
391 #define PCI_PCIX_BRIDGE_STATUS_64BIT 0x00010000
392 #define PCI_PCIX_BRIDGE_STATUS_133MHZ 0x00020000
393 #define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */
394 #define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */
395 #define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN 0x00100000 /* Split Completion Overrun */
396 #define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED 0x00200000
397 #define PCI_PCIX_BRIDGE_STATUS_RESERVED 0xffc00000
398 #define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL 8 /* Upstream Split Transaction Register offset */
399 #define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL 12 /* Downstream Split Transaction Register offset */
400 #define PCI_PCIX_BRIDGE_STR_CAPACITY 0x0000ffff
401 #define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT 0xffff0000
402 #define PCI_PCIX_BRIDGE_SIZEOF 12
404 /* HyperTransport (as of spec rev. 2.00) */
405 #define PCI_HT_CMD 2 /* Command Register */
406 #define PCI_HT_CMD_TYP_HI 0xe000 /* Capability Type high part */
407 #define PCI_HT_CMD_TYP_HI_PRI 0x0000 /* Slave or Primary Interface */
408 #define PCI_HT_CMD_TYP_HI_SEC 0x2000 /* Host or Secondary Interface */
409 #define PCI_HT_CMD_TYP 0xf800 /* Capability Type */
410 #define PCI_HT_CMD_TYP_SW 0x4000 /* Switch */
411 #define PCI_HT_CMD_TYP_IDC 0x8000 /* Interrupt Discovery and Configuration */
412 #define PCI_HT_CMD_TYP_RID 0x8800 /* Revision ID */
413 #define PCI_HT_CMD_TYP_UIDC 0x9000 /* UnitID Clumping */
414 #define PCI_HT_CMD_TYP_ECSA 0x9800 /* Extended Configuration Space Access */
415 #define PCI_HT_CMD_TYP_AM 0xa000 /* Address Mapping */
416 #define PCI_HT_CMD_TYP_MSIM 0xa800 /* MSI Mapping */
417 #define PCI_HT_CMD_TYP_DR 0xb000 /* DirectRoute */
418 #define PCI_HT_CMD_TYP_VCS 0xb800 /* VCSet */
419 #define PCI_HT_CMD_TYP_RM 0xc000 /* Retry Mode */
420 #define PCI_HT_CMD_TYP_X86 0xc800 /* X86 (reserved) */
422 /* Link Control Register */
423 #define PCI_HT_LCTR_CFLE 0x0002 /* CRC Flood Enable */
424 #define PCI_HT_LCTR_CST 0x0004 /* CRC Start Test */
425 #define PCI_HT_LCTR_CFE 0x0008 /* CRC Force Error */
426 #define PCI_HT_LCTR_LKFAIL 0x0010 /* Link Failure */
427 #define PCI_HT_LCTR_INIT 0x0020 /* Initialization Complete */
428 #define PCI_HT_LCTR_EOC 0x0040 /* End of Chain */
429 #define PCI_HT_LCTR_TXO 0x0080 /* Transmitter Off */
430 #define PCI_HT_LCTR_CRCERR 0x0f00 /* CRC Error */
431 #define PCI_HT_LCTR_ISOCEN 0x1000 /* Isochronous Flow Control Enable */
432 #define PCI_HT_LCTR_LSEN 0x2000 /* LDTSTOP# Tristate Enable */
433 #define PCI_HT_LCTR_EXTCTL 0x4000 /* Extended CTL Time */
434 #define PCI_HT_LCTR_64B 0x8000 /* 64-bit Addressing Enable */
436 /* Link Configuration Register */
437 #define PCI_HT_LCNF_MLWI 0x0007 /* Max Link Width In */
438 #define PCI_HT_LCNF_LW_8B 0x0 /* Link Width 8 bits */
439 #define PCI_HT_LCNF_LW_16B 0x1 /* Link Width 16 bits */
440 #define PCI_HT_LCNF_LW_32B 0x3 /* Link Width 32 bits */
441 #define PCI_HT_LCNF_LW_2B 0x4 /* Link Width 2 bits */
442 #define PCI_HT_LCNF_LW_4B 0x5 /* Link Width 4 bits */
443 #define PCI_HT_LCNF_LW_NC 0x7 /* Link physically not connected */
444 #define PCI_HT_LCNF_DFI 0x0008 /* Doubleword Flow Control In */
445 #define PCI_HT_LCNF_MLWO 0x0070 /* Max Link Width Out */
446 #define PCI_HT_LCNF_DFO 0x0080 /* Doubleword Flow Control Out */
447 #define PCI_HT_LCNF_LWI 0x0700 /* Link Width In */
448 #define PCI_HT_LCNF_DFIE 0x0800 /* Doubleword Flow Control In Enable */
449 #define PCI_HT_LCNF_LWO 0x7000 /* Link Width Out */
450 #define PCI_HT_LCNF_DFOE 0x8000 /* Doubleword Flow Control Out Enable */
452 /* Revision ID Register */
453 #define PCI_HT_RID_MIN 0x1f /* Minor Revision */
454 #define PCI_HT_RID_MAJ 0xe0 /* Major Revision */
456 /* Link Frequency/Error Register */
457 #define PCI_HT_LFRER_FREQ 0x0f /* Transmitter Clock Frequency */
458 #define PCI_HT_LFRER_200 0x00 /* 200MHz */
459 #define PCI_HT_LFRER_300 0x01 /* 300MHz */
460 #define PCI_HT_LFRER_400 0x02 /* 400MHz */
461 #define PCI_HT_LFRER_500 0x03 /* 500MHz */
462 #define PCI_HT_LFRER_600 0x04 /* 600MHz */
463 #define PCI_HT_LFRER_800 0x05 /* 800MHz */
464 #define PCI_HT_LFRER_1000 0x06 /* 1.0GHz */
465 #define PCI_HT_LFRER_1200 0x07 /* 1.2GHz */
466 #define PCI_HT_LFRER_1400 0x08 /* 1.4GHz */
467 #define PCI_HT_LFRER_1600 0x09 /* 1.6GHz */
468 #define PCI_HT_LFRER_VEND 0x0f /* Vendor-Specific */
469 #define PCI_HT_LFRER_ERR 0xf0 /* Link Error */
470 #define PCI_HT_LFRER_PROT 0x10 /* Protocol Error */
471 #define PCI_HT_LFRER_OV 0x20 /* Overflow Error */
472 #define PCI_HT_LFRER_EOC 0x40 /* End of Chain Error */
473 #define PCI_HT_LFRER_CTLT 0x80 /* CTL Timeout */
475 /* Link Frequency Capability Register */
476 #define PCI_HT_LFCAP_200 0x0001 /* 200MHz */
477 #define PCI_HT_LFCAP_300 0x0002 /* 300MHz */
478 #define PCI_HT_LFCAP_400 0x0004 /* 400MHz */
479 #define PCI_HT_LFCAP_500 0x0008 /* 500MHz */
480 #define PCI_HT_LFCAP_600 0x0010 /* 600MHz */
481 #define PCI_HT_LFCAP_800 0x0020 /* 800MHz */
482 #define PCI_HT_LFCAP_1000 0x0040 /* 1.0GHz */
483 #define PCI_HT_LFCAP_1200 0x0080 /* 1.2GHz */
484 #define PCI_HT_LFCAP_1400 0x0100 /* 1.4GHz */
485 #define PCI_HT_LFCAP_1600 0x0200 /* 1.6GHz */
486 #define PCI_HT_LFCAP_VEND 0x8000 /* Vendor-Specific */
488 /* Feature Register */
489 #define PCI_HT_FTR_ISOCFC 0x0001 /* Isochronous Flow Control Mode */
490 #define PCI_HT_FTR_LDTSTOP 0x0002 /* LDTSTOP# Supported */
491 #define PCI_HT_FTR_CRCTM 0x0004 /* CRC Test Mode */
492 #define PCI_HT_FTR_ECTLT 0x0008 /* Extended CTL Time Required */
493 #define PCI_HT_FTR_64BA 0x0010 /* 64-bit Addressing */
494 #define PCI_HT_FTR_UIDRD 0x0020 /* UnitID Reorder Disable */
496 /* Error Handling Register */
497 #define PCI_HT_EH_PFLE 0x0001 /* Protocol Error Flood Enable */
498 #define PCI_HT_EH_OFLE 0x0002 /* Overflow Error Flood Enable */
499 #define PCI_HT_EH_PFE 0x0004 /* Protocol Error Fatal Enable */
500 #define PCI_HT_EH_OFE 0x0008 /* Overflow Error Fatal Enable */
501 #define PCI_HT_EH_EOCFE 0x0010 /* End of Chain Error Fatal Enable */
502 #define PCI_HT_EH_RFE 0x0020 /* Response Error Fatal Enable */
503 #define PCI_HT_EH_CRCFE 0x0040 /* CRC Error Fatal Enable */
504 #define PCI_HT_EH_SERRFE 0x0080 /* System Error Fatal Enable (B */
505 #define PCI_HT_EH_CF 0x0100 /* Chain Fail */
506 #define PCI_HT_EH_RE 0x0200 /* Response Error */
507 #define PCI_HT_EH_PNFE 0x0400 /* Protocol Error Nonfatal Enable */
508 #define PCI_HT_EH_ONFE 0x0800 /* Overflow Error Nonfatal Enable */
509 #define PCI_HT_EH_EOCNFE 0x1000 /* End of Chain Error Nonfatal Enable */
510 #define PCI_HT_EH_RNFE 0x2000 /* Response Error Nonfatal Enable */
511 #define PCI_HT_EH_CRCNFE 0x4000 /* CRC Error Nonfatal Enable */
512 #define PCI_HT_EH_SERRNFE 0x8000 /* System Error Nonfatal Enable */
514 /* HyperTransport: Slave or Primary Interface */
515 #define PCI_HT_PRI_CMD 2 /* Command Register */
516 #define PCI_HT_PRI_CMD_BUID 0x001f /* Base UnitID */
517 #define PCI_HT_PRI_CMD_UC 0x03e0 /* Unit Count */
518 #define PCI_HT_PRI_CMD_MH 0x0400 /* Master Host */
519 #define PCI_HT_PRI_CMD_DD 0x0800 /* Default Direction */
520 #define PCI_HT_PRI_CMD_DUL 0x1000 /* Drop on Uninitialized Link */
522 #define PCI_HT_PRI_LCTR0 4 /* Link Control 0 Register */
523 #define PCI_HT_PRI_LCNF0 6 /* Link Config 0 Register */
524 #define PCI_HT_PRI_LCTR1 8 /* Link Control 1 Register */
525 #define PCI_HT_PRI_LCNF1 10 /* Link Config 1 Register */
526 #define PCI_HT_PRI_RID 12 /* Revision ID Register */
527 #define PCI_HT_PRI_LFRER0 13 /* Link Frequency/Error 0 Register */
528 #define PCI_HT_PRI_LFCAP0 14 /* Link Frequency Capability 0 Register */
529 #define PCI_HT_PRI_FTR 16 /* Feature Register */
530 #define PCI_HT_PRI_LFRER1 17 /* Link Frequency/Error 1 Register */
531 #define PCI_HT_PRI_LFCAP1 18 /* Link Frequency Capability 1 Register */
532 #define PCI_HT_PRI_ES 20 /* Enumeration Scratchpad Register */
533 #define PCI_HT_PRI_EH 22 /* Error Handling Register */
534 #define PCI_HT_PRI_MBU 24 /* Memory Base Upper Register */
535 #define PCI_HT_PRI_MLU 25 /* Memory Limit Upper Register */
536 #define PCI_HT_PRI_BN 26 /* Bus Number Register */
537 #define PCI_HT_PRI_SIZEOF 28
539 /* HyperTransport: Host or Secondary Interface */
540 #define PCI_HT_SEC_CMD 2 /* Command Register */
541 #define PCI_HT_SEC_CMD_WR 0x0001 /* Warm Reset */
542 #define PCI_HT_SEC_CMD_DE 0x0002 /* Double-Ended */
543 #define PCI_HT_SEC_CMD_DN 0x007c /* Device Number */
544 #define PCI_HT_SEC_CMD_CS 0x0080 /* Chain Side */
545 #define PCI_HT_SEC_CMD_HH 0x0100 /* Host Hide */
546 #define PCI_HT_SEC_CMD_AS 0x0400 /* Act as Slave */
547 #define PCI_HT_SEC_CMD_HIECE 0x0800 /* Host Inbound End of Chain Error */
548 #define PCI_HT_SEC_CMD_DUL 0x1000 /* Drop on Uninitialized Link */
550 #define PCI_HT_SEC_LCTR 4 /* Link Control Register */
551 #define PCI_HT_SEC_LCNF 6 /* Link Config Register */
552 #define PCI_HT_SEC_RID 8 /* Revision ID Register */
553 #define PCI_HT_SEC_LFRER 9 /* Link Frequency/Error Register */
554 #define PCI_HT_SEC_LFCAP 10 /* Link Frequency Capability Register */
555 #define PCI_HT_SEC_FTR 12 /* Feature Register */
556 #define PCI_HT_SEC_FTR_EXTRS 0x0100 /* Extended Register Set */
557 #define PCI_HT_SEC_FTR_UCNFE 0x0200 /* Upstream Configuration Enable */
558 #define PCI_HT_SEC_ES 16 /* Enumeration Scratchpad Register */
559 #define PCI_HT_SEC_EH 18 /* Error Handling Register */
560 #define PCI_HT_SEC_MBU 20 /* Memory Base Upper Register */
561 #define PCI_HT_SEC_MLU 21 /* Memory Limit Upper Register */
562 #define PCI_HT_SEC_SIZEOF 24
564 /* HyperTransport: Switch */
565 #define PCI_HT_SW_CMD 2 /* Switch Command Register */
566 #define PCI_HT_SW_CMD_VIBERR 0x0080 /* VIB Error */
567 #define PCI_HT_SW_CMD_VIBFL 0x0100 /* VIB Flood */
568 #define PCI_HT_SW_CMD_VIBFT 0x0200 /* VIB Fatal */
569 #define PCI_HT_SW_CMD_VIBNFT 0x0400 /* VIB Nonfatal */
570 #define PCI_HT_SW_PMASK 4 /* Partition Mask Register */
571 #define PCI_HT_SW_SWINF 8 /* Switch Info Register */
572 #define PCI_HT_SW_SWINF_DP 0x0000001f /* Default Port */
573 #define PCI_HT_SW_SWINF_EN 0x00000020 /* Enable Decode */
574 #define PCI_HT_SW_SWINF_CR 0x00000040 /* Cold Reset */
575 #define PCI_HT_SW_SWINF_PCIDX 0x00000f00 /* Performance Counter Index */
576 #define PCI_HT_SW_SWINF_BLRIDX 0x0003f000 /* Base/Limit Range Index */
577 #define PCI_HT_SW_SWINF_SBIDX 0x00002000 /* Secondary Base Range Index */
578 #define PCI_HT_SW_SWINF_HP 0x00040000 /* Hot Plug */
579 #define PCI_HT_SW_SWINF_HIDE 0x00080000 /* Hide Port */
580 #define PCI_HT_SW_PCD 12 /* Performance Counter Data Register */
581 #define PCI_HT_SW_BLRD 16 /* Base/Limit Range Data Register */
582 #define PCI_HT_SW_SBD 20 /* Secondary Base Data Register */
583 #define PCI_HT_SW_SIZEOF 24
585 /* Counter indices */
586 #define PCI_HT_SW_PC_PCR 0x0 /* Posted Command Receive */
587 #define PCI_HT_SW_PC_NPCR 0x1 /* Nonposted Command Receive */
588 #define PCI_HT_SW_PC_RCR 0x2 /* Response Command Receive */
589 #define PCI_HT_SW_PC_PDWR 0x3 /* Posted DW Receive */
590 #define PCI_HT_SW_PC_NPDWR 0x4 /* Nonposted DW Receive */
591 #define PCI_HT_SW_PC_RDWR 0x5 /* Response DW Receive */
592 #define PCI_HT_SW_PC_PCT 0x6 /* Posted Command Transmit */
593 #define PCI_HT_SW_PC_NPCT 0x7 /* Nonposted Command Transmit */
594 #define PCI_HT_SW_PC_RCT 0x8 /* Response Command Transmit */
595 #define PCI_HT_SW_PC_PDWT 0x9 /* Posted DW Transmit */
596 #define PCI_HT_SW_PC_NPDWT 0xa /* Nonposted DW Transmit */
597 #define PCI_HT_SW_PC_RDWT 0xb /* Response DW Transmit */
599 /* Base/Limit Range indices */
600 #define PCI_HT_SW_BLR_BASE0_LO 0x0 /* Base 0[31:1], Enable */
601 #define PCI_HT_SW_BLR_BASE0_HI 0x1 /* Base 0 Upper */
602 #define PCI_HT_SW_BLR_LIM0_LO 0x2 /* Limit 0 Lower */
603 #define PCI_HT_SW_BLR_LIM0_HI 0x3 /* Limit 0 Upper */
605 /* Secondary Base indices */
606 #define PCI_HT_SW_SB_LO 0x0 /* Secondary Base[31:1], Enable */
607 #define PCI_HT_SW_S0_HI 0x1 /* Secondary Base Upper */
609 /* HyperTransport: Interrupt Discovery and Configuration */
610 #define PCI_HT_IDC_IDX 2 /* Index Register */
611 #define PCI_HT_IDC_DATA 4 /* Data Register */
612 #define PCI_HT_IDC_SIZEOF 8
614 /* Register indices */
615 #define PCI_HT_IDC_IDX_LINT 0x01 /* Last Interrupt Register */
616 #define PCI_HT_IDC_LINT 0x00ff0000 /* Last interrupt definition */
617 #define PCI_HT_IDC_IDX_IDR 0x10 /* Interrupt Definition Registers */
618 /* Low part (at index) */
619 #define PCI_HT_IDC_IDR_MASK 0x10000001 /* Mask */
620 #define PCI_HT_IDC_IDR_POL 0x10000002 /* Polarity */
621 #define PCI_HT_IDC_IDR_II_2 0x1000001c /* IntrInfo[4:2]: Message Type */
622 #define PCI_HT_IDC_IDR_II_5 0x10000020 /* IntrInfo[5]: Request EOI */
623 #define PCI_HT_IDC_IDR_II_6 0x00ffffc0 /* IntrInfo[23:6] */
624 #define PCI_HT_IDC_IDR_II_24 0xff000000 /* IntrInfo[31:24] */
625 /* High part (at index + 1) */
626 #define PCI_HT_IDC_IDR_II_32 0x00ffffff /* IntrInfo[55:32] */
627 #define PCI_HT_IDC_IDR_PASSPW 0x40000000 /* PassPW setting for messages */
628 #define PCI_HT_IDC_IDR_WEOI 0x80000000 /* Waiting for EOI */
630 /* HyperTransport: Revision ID */
631 #define PCI_HT_RID_RID 2 /* Revision Register */
632 #define PCI_HT_RID_SIZEOF 4
634 /* HyperTransport: UnitID Clumping */
635 #define PCI_HT_UIDC_CS 4 /* Clumping Support Register */
636 #define PCI_HT_UIDC_CE 8 /* Clumping Enable Register */
637 #define PCI_HT_UIDC_SIZEOF 12
639 /* HyperTransport: Extended Configuration Space Access */
640 #define PCI_HT_ECSA_ADDR 4 /* Configuration Address Register */
641 #define PCI_HT_ECSA_ADDR_REG 0x00000ffc /* Register */
642 #define PCI_HT_ECSA_ADDR_FUN 0x00007000 /* Function */
643 #define PCI_HT_ECSA_ADDR_DEV 0x000f1000 /* Device */
644 #define PCI_HT_ECSA_ADDR_BUS 0x0ff00000 /* Bus Number */
645 #define PCI_HT_ECSA_ADDR_TYPE 0x10000000 /* Access Type */
646 #define PCI_HT_ECSA_DATA 8 /* Configuration Data Register */
647 #define PCI_HT_ECSA_SIZEOF 12
649 /* HyperTransport: Address Mapping */
650 #define PCI_HT_AM_CMD 2 /* Command Register */
651 #define PCI_HT_AM_CMD_NDMA 0x000f /* Number of DMA Mappings */
652 #define PCI_HT_AM_CMD_IOSIZ 0x01f0 /* I/O Size */
653 #define PCI_HT_AM_CMD_MT 0x0600 /* Map Type */
654 #define PCI_HT_AM_CMD_MT_40B 0x0000 /* 40-bit */
655 #define PCI_HT_AM_CMD_MT_64B 0x0200 /* 64-bit */
657 /* Window Control Register bits */
658 #define PCI_HT_AM_SBW_CTR_COMP 0x1 /* Compat */
659 #define PCI_HT_AM_SBW_CTR_NCOH 0x2 /* NonCoherent */
660 #define PCI_HT_AM_SBW_CTR_ISOC 0x4 /* Isochronous */
661 #define PCI_HT_AM_SBW_CTR_EN 0x8 /* Enable */
663 /* HyperTransport: 40-bit Address Mapping */
664 #define PCI_HT_AM40_SBNPW 4 /* Secondary Bus Non-Prefetchable Window Register */
665 #define PCI_HT_AM40_SBW_BASE 0x000fffff /* Window Base */
666 #define PCI_HT_AM40_SBW_CTR 0xf0000000 /* Window Control */
667 #define PCI_HT_AM40_SBPW 8 /* Secondary Bus Prefetchable Window Register */
668 #define PCI_HT_AM40_DMA_PBASE0 12 /* DMA Window Primary Base 0 Register */
669 #define PCI_HT_AM40_DMA_CTR0 15 /* DMA Window Control 0 Register */
670 #define PCI_HT_AM40_DMA_CTR_CTR 0xf0 /* Window Control */
671 #define PCI_HT_AM40_DMA_SLIM0 16 /* DMA Window Secondary Limit 0 Register */
672 #define PCI_HT_AM40_DMA_SBASE0 18 /* DMA Window Secondary Base 0 Register */
673 #define PCI_HT_AM40_SIZEOF 12 /* size is variable: 12 + 8 * NDMA */
675 /* HyperTransport: 64-bit Address Mapping */
676 #define PCI_HT_AM64_IDX 4 /* Index Register */
677 #define PCI_HT_AM64_DATA_LO 8 /* Data Lower Register */
678 #define PCI_HT_AM64_DATA_HI 12 /* Data Upper Register */
679 #define PCI_HT_AM64_SIZEOF 16
681 /* Register indices */
682 #define PCI_HT_AM64_IDX_SBNPW 0x00 /* Secondary Bus Non-Prefetchable Window Register */
683 #define PCI_HT_AM64_W_BASE_LO 0xfff00000 /* Window Base Lower */
684 #define PCI_HT_AM64_W_CTR 0x0000000f /* Window Control */
685 #define PCI_HT_AM64_IDX_SBPW 0x01 /* Secondary Bus Prefetchable Window Register */
686 #define PCI_HT_AM64_IDX_PBNPW 0x02 /* Primary Bus Non-Prefetchable Window Register */
687 #define PCI_HT_AM64_IDX_DMAPB0 0x04 /* DMA Window Primary Base 0 Register */
688 #define PCI_HT_AM64_IDX_DMASB0 0x05 /* DMA Window Secondary Base 0 Register */
689 #define PCI_HT_AM64_IDX_DMASL0 0x06 /* DMA Window Secondary Limit 0 Register */
691 /* HyperTransport: MSI Mapping */
692 #define PCI_HT_MSIM_CMD 2 /* Command Register */
693 #define PCI_HT_MSIM_CMD_EN 0x0001 /* Mapping Active */
694 #define PCI_HT_MSIM_CMD_FIXD 0x0002 /* MSI Mapping Address Fixed */
695 #define PCI_HT_MSIM_ADDR_LO 4 /* MSI Mapping Address Lower Register */
696 #define PCI_HT_MSIM_ADDR_HI 8 /* MSI Mapping Address Upper Register */
697 #define PCI_HT_MSIM_SIZEOF 12
699 /* HyperTransport: DirectRoute */
700 #define PCI_HT_DR_CMD 2 /* Command Register */
701 #define PCI_HT_DR_CMD_NDRS 0x000f /* Number of DirectRoute Spaces */
702 #define PCI_HT_DR_CMD_IDX 0x01f0 /* Index */
703 #define PCI_HT_DR_EN 4 /* Enable Vector Register */
704 #define PCI_HT_DR_DATA 8 /* Data Register */
705 #define PCI_HT_DR_SIZEOF 12
707 /* Register indices */
708 #define PCI_HT_DR_IDX_BASE_LO 0x00 /* DirectRoute Base Lower Register */
709 #define PCI_HT_DR_OTNRD 0x00000001 /* Opposite to Normal Request Direction */
710 #define PCI_HT_DR_BL_LO 0xffffff00 /* Base/Limit Lower */
711 #define PCI_HT_DR_IDX_BASE_HI 0x01 /* DirectRoute Base Upper Register */
712 #define PCI_HT_DR_IDX_LIMIT_LO 0x02 /* DirectRoute Limit Lower Register */
713 #define PCI_HT_DR_IDX_LIMIT_HI 0x03 /* DirectRoute Limit Upper Register */
715 /* HyperTransport: VCSet */
716 #define PCI_HT_VCS_SUP 4 /* VCSets Supported Register */
717 #define PCI_HT_VCS_L1EN 5 /* Link 1 VCSets Enabled Register */
718 #define PCI_HT_VCS_L0EN 6 /* Link 0 VCSets Enabled Register */
719 #define PCI_HT_VCS_SBD 8 /* Stream Bucket Depth Register */
720 #define PCI_HT_VCS_SINT 9 /* Stream Interval Register */
721 #define PCI_HT_VCS_SSUP 10 /* Number of Streaming VCs Supported Register */
722 #define PCI_HT_VCS_SSUP_0 0x00 /* Streaming VC 0 */
723 #define PCI_HT_VCS_SSUP_3 0x01 /* Streaming VCs 0-3 */
724 #define PCI_HT_VCS_SSUP_15 0x02 /* Streaming VCs 0-15 */
725 #define PCI_HT_VCS_NFCBD 12 /* Non-FC Bucket Depth Register */
726 #define PCI_HT_VCS_NFCINT 13 /* Non-FC Bucket Interval Register */
727 #define PCI_HT_VCS_SIZEOF 16
729 /* HyperTransport: Retry Mode */
730 #define PCI_HT_RM_CTR0 4 /* Control 0 Register */
731 #define PCI_HT_RM_CTR_LRETEN 0x01 /* Link Retry Enable */
732 #define PCI_HT_RM_CTR_FSER 0x02 /* Force Single Error */
733 #define PCI_HT_RM_CTR_ROLNEN 0x04 /* Rollover Nonfatal Enable */
734 #define PCI_HT_RM_CTR_FSS 0x08 /* Force Single Stomp */
735 #define PCI_HT_RM_CTR_RETNEN 0x10 /* Retry Nonfatal Enable */
736 #define PCI_HT_RM_CTR_RETFEN 0x20 /* Retry Fatal Enable */
737 #define PCI_HT_RM_CTR_AA 0xc0 /* Allowed Attempts */
738 #define PCI_HT_RM_STS0 5 /* Status 0 Register */
739 #define PCI_HT_RM_STS_RETSNT 0x01 /* Retry Sent */
740 #define PCI_HT_RM_STS_CNTROL 0x02 /* Count Rollover */
741 #define PCI_HT_RM_STS_SRCV 0x04 /* Stomp Received */
742 #define PCI_HT_RM_CTR1 6 /* Control 1 Register */
743 #define PCI_HT_RM_STS1 7 /* Status 1 Register */
744 #define PCI_HT_RM_CNT0 8 /* Retry Count 0 Register */
745 #define PCI_HT_RM_CNT1 10 /* Retry Count 1 Register */
746 #define PCI_HT_RM_SIZEOF 12
748 /* Vendor-Specific Capability (see PCI_EVNDR_xxx for the PCIe version) */
749 #define PCI_VNDR_LENGTH 2 /* Length byte */
752 #define PCI_EXP_FLAGS 0x2 /* Capabilities register */
753 #define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
754 #define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
755 #define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
756 #define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
757 #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
758 #define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
759 #define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
760 #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */
761 #define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */
762 #define PCI_EXP_TYPE_ROOT_INT_EP 0x9 /* Root Complex Integrated Endpoint */
763 #define PCI_EXP_TYPE_ROOT_EC 0xa /* Root Complex Event Collector */
764 #define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
765 #define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
766 #define PCI_EXP_DEVCAP 0x4 /* Device capabilities */
767 #define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
768 #define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
769 #define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
770 #define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
771 #define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
772 #define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
773 #define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
774 #define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
775 #define PCI_EXP_DEVCAP_RBE 0x8000 /* Role-Based Error Reporting */
776 #define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
777 #define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
778 #define PCI_EXP_DEVCAP_FLRESET 0x10000000 /* Function-Level Reset */
779 #define PCI_EXP_DEVCTL 0x8 /* Device Control */
780 #define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
781 #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
782 #define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
783 #define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
784 #define PCI_EXP_DEVCTL_RELAXED 0x0010 /* Enable Relaxed Ordering */
785 #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
786 #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
787 #define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
788 #define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
789 #define PCI_EXP_DEVCTL_NOSNOOP 0x0800 /* Enable No Snoop */
790 #define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
791 #define PCI_EXP_DEVCTL_BCRE 0x8000 /* Bridge Configuration Retry Enable */
792 #define PCI_EXP_DEVCTL_FLRESET 0x8000 /* Function-Level Reset [bit shared with BCRE] */
793 #define PCI_EXP_DEVSTA 0xa /* Device Status */
794 #define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
795 #define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
796 #define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
797 #define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
798 #define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
799 #define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
800 #define PCI_EXP_LNKCAP 0xc /* Link Capabilities */
801 #define PCI_EXP_LNKCAP_SPEED 0x0000f /* Maximum Link Speed */
802 #define PCI_EXP_LNKCAP_WIDTH 0x003f0 /* Maximum Link Width */
803 #define PCI_EXP_LNKCAP_ASPM 0x00c00 /* Active State Power Management */
804 #define PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Exit Latency */
805 #define PCI_EXP_LNKCAP_L1 0x38000 /* L1 Exit Latency */
806 #define PCI_EXP_LNKCAP_CLOCKPM 0x40000 /* Clock Power Management */
807 #define PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting */
808 #define PCI_EXP_LNKCAP_DLLA 0x100000 /* Data Link Layer Active Reporting */
809 #define PCI_EXP_LNKCAP_LBNC 0x200000 /* Link Bandwidth Notification Capability */
810 #define PCI_EXP_LNKCAP_AOC 0x400000 /* ASPM Optionality Compliance */
811 #define PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */
812 #define PCI_EXP_LNKCTL 0x10 /* Link Control */
813 #define PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */
814 #define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */
815 #define PCI_EXP_LNKCTL_DISABLE 0x0010 /* Link Disable */
816 #define PCI_EXP_LNKCTL_RETRAIN 0x0020 /* Retrain Link */
817 #define PCI_EXP_LNKCTL_CLOCK 0x0040 /* Common Clock Configuration */
818 #define PCI_EXP_LNKCTL_XSYNCH 0x0080 /* Extended Synch */
819 #define PCI_EXP_LNKCTL_CLOCKPM 0x0100 /* Clock Power Management */
820 #define PCI_EXP_LNKCTL_HWAUTWD 0x0200 /* Hardware Autonomous Width Disable */
821 #define PCI_EXP_LNKCTL_BWMIE 0x0400 /* Bandwidth Mgmt Interrupt Enable */
822 #define PCI_EXP_LNKCTL_AUTBWIE 0x0800 /* Autonomous Bandwidth Mgmt Interrupt Enable */
823 #define PCI_EXP_LNKSTA 0x12 /* Link Status */
824 #define PCI_EXP_LNKSTA_SPEED 0x000f /* Negotiated Link Speed */
825 #define PCI_EXP_LNKSTA_WIDTH 0x03f0 /* Negotiated Link Width */
826 #define PCI_EXP_LNKSTA_TR_ERR 0x0400 /* Training Error (obsolete) */
827 #define PCI_EXP_LNKSTA_TRAIN 0x0800 /* Link Training */
828 #define PCI_EXP_LNKSTA_SL_CLK 0x1000 /* Slot Clock Configuration */
829 #define PCI_EXP_LNKSTA_DL_ACT 0x2000 /* Data Link Layer in DL_Active State */
830 #define PCI_EXP_LNKSTA_BWMGMT 0x4000 /* Bandwidth Mgmt Status */
831 #define PCI_EXP_LNKSTA_AUTBW 0x8000 /* Autonomous Bandwidth Mgmt Status */
832 #define PCI_EXP_SLTCAP 0x14 /* Slot Capabilities */
833 #define PCI_EXP_SLTCAP_ATNB 0x0001 /* Attention Button Present */
834 #define PCI_EXP_SLTCAP_PWRC 0x0002 /* Power Controller Present */
835 #define PCI_EXP_SLTCAP_MRL 0x0004 /* MRL Sensor Present */
836 #define PCI_EXP_SLTCAP_ATNI 0x0008 /* Attention Indicator Present */
837 #define PCI_EXP_SLTCAP_PWRI 0x0010 /* Power Indicator Present */
838 #define PCI_EXP_SLTCAP_HPS 0x0020 /* Hot-Plug Surprise */
839 #define PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */
840 #define PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 /* Slot Power Limit Value */
841 #define PCI_EXP_SLTCAP_PWR_SCL 0x00018000 /* Slot Power Limit Scale */
842 #define PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock Present */
843 #define PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support */
844 #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
845 #define PCI_EXP_SLTCTL 0x18 /* Slot Control */
846 #define PCI_EXP_SLTCTL_ATNB 0x0001 /* Attention Button Pressed Enable */
847 #define PCI_EXP_SLTCTL_PWRF 0x0002 /* Power Fault Detected Enable */
848 #define PCI_EXP_SLTCTL_MRLS 0x0004 /* MRL Sensor Changed Enable */
849 #define PCI_EXP_SLTCTL_PRSD 0x0008 /* Presence Detect Changed Enable */
850 #define PCI_EXP_SLTCTL_CMDC 0x0010 /* Command Completed Interrupt Enable */
851 #define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
852 #define PCI_EXP_SLTCTL_ATNI 0x00c0 /* Attention Indicator Control */
853 #define PCI_EXP_SLTCTL_PWRI 0x0300 /* Power Indicator Control */
854 #define PCI_EXP_SLTCTL_PWRC 0x0400 /* Power Controller Control */
855 #define PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Control */
856 #define PCI_EXP_SLTCTL_LLCHG 0x1000 /* Data Link Layer State Changed Enable */
857 #define PCI_EXP_SLTSTA 0x1a /* Slot Status */
858 #define PCI_EXP_SLTSTA_ATNB 0x0001 /* Attention Button Pressed */
859 #define PCI_EXP_SLTSTA_PWRF 0x0002 /* Power Fault Detected */
860 #define PCI_EXP_SLTSTA_MRLS 0x0004 /* MRL Sensor Changed */
861 #define PCI_EXP_SLTSTA_PRSD 0x0008 /* Presence Detect Changed */
862 #define PCI_EXP_SLTSTA_CMDC 0x0010 /* Command Completed */
863 #define PCI_EXP_SLTSTA_MRL_ST 0x0020 /* MRL Sensor State */
864 #define PCI_EXP_SLTSTA_PRES 0x0040 /* Presence Detect State */
865 #define PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Status */
866 #define PCI_EXP_SLTSTA_LLCHG 0x0100 /* Data Link Layer State Changed */
867 #define PCI_EXP_RTCTL 0x1c /* Root Control */
868 #define PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error */
869 #define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */
870 #define PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */
871 #define PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */
872 #define PCI_EXP_RTCTL_CRSVIS 0x0010 /* Configuration Request Retry Status Visible to SW */
873 #define PCI_EXP_RTCAP 0x1e /* Root Capabilities */
874 #define PCI_EXP_RTCAP_CRSVIS 0x0001 /* Configuration Request Retry Status Visible to SW */
875 #define PCI_EXP_RTSTA 0x20 /* Root Status */
876 #define PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */
877 #define PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */
878 #define PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
879 #define PCI_EXP_DEVCAP2 0x24 /* Device capabilities 2 */
880 #define PCI_EXP_DEVCAP2_TIMEOUT_RANGE(x) ((x) & 0xf) /* Completion Timeout Ranges Supported */
881 #define PCI_EXP_DEVCAP2_TIMEOUT_DIS 0x0010 /* Completion Timeout Disable Supported */
882 #define PCI_EXP_DEVCAP2_ARI 0x0020 /* ARI Forwarding Supported */
883 #define PCI_EXP_DEVCAP2_ATOMICOP_ROUTING 0x0040 /* AtomicOp Routing Supported */
884 #define PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP 0x0080 /* 32bit AtomicOp Completer Supported */
885 #define PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP 0x0100 /* 64bit AtomicOp Completer Supported */
886 #define PCI_EXP_DEVCAP2_128BIT_CAS_COMP 0x0200 /* 128bit CAS Completer Supported */
887 #define PCI_EXP_DEVCAP2_NROPRPRP 0x0400 /* No RO-enabled PR-PR Passing */
888 #define PCI_EXP_DEVCAP2_LTR 0x0800 /* LTR supported */
889 #define PCI_EXP_DEVCAP2_TPH_COMP(x) (((x) >> 12) & 3) /* TPH Completer Supported */
890 #define PCI_EXP_DEVCAP2_LN_CLS(x) (((x) >> 14) & 3) /* LN System CLS Supported */
891 #define PCI_EXP_DEVCAP2_10BIT_TAG_COMP 0x00010000 /* 10 Bit Tag Completer */
892 #define PCI_EXP_DEVCAP2_10BIT_TAG_REQ 0x00020000 /* 10 Bit Tag Requester */
893 #define PCI_EXP_DEVCAP2_OBFF(x) (((x) >> 18) & 3) /* OBFF supported */
894 #define PCI_EXP_DEVCAP2_EXTFMT 0x00100000 /* Extended Fmt Field Supported */
895 #define PCI_EXP_DEVCAP2_EE_TLP 0x00200000 /* End-End TLP Prefix Supported */
896 #define PCI_EXP_DEVCAP2_MEE_TLP(x) (((x) >> 22) & 3) /* Max End-End TLP Prefixes */
897 #define PCI_EXP_DEVCAP2_EPR(x) (((x) >> 24) & 3) /* Emergency Power Reduction Supported */
898 #define PCI_EXP_DEVCAP2_EPR_INIT 0x04000000 /* Emergency Power Reduction Initialization Required */
899 #define PCI_EXP_DEVCAP2_FRS 0x80000000 /* FRS supported */
900 #define PCI_EXP_DEVCTL2 0x28 /* Device Control */
901 #define PCI_EXP_DEVCTL2_TIMEOUT_VALUE(x) ((x) & 0xf) /* Completion Timeout Value */
902 #define PCI_EXP_DEVCTL2_TIMEOUT_DIS 0x0010 /* Completion Timeout Disable */
903 #define PCI_EXP_DEVCTL2_ARI 0x0020 /* ARI Forwarding */
904 #define PCI_EXP_DEVCTL2_ATOMICOP_REQUESTER_EN 0x0040 /* AtomicOp RequesterEnable */
905 #define PCI_EXP_DEVCTL2_ATOMICOP_EGRESS_BLOCK 0x0080 /* AtomicOp Egress Blocking */
906 #define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */
907 #define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */
908 #define PCI_EXP_DEVCTL2_LTR 0x0400 /* LTR enabled */
909 #define PCI_EXP_DEVCTL2_EPR_REQ 0x0800 /* Emergency Power Reduction Request */
910 #define PCI_EXP_DEVCTL2_10BIT_TAG_REQ 0x1000 /* 10 Bit Tag Requester enabled */
911 #define PCI_EXP_DEVCTL2_OBFF(x) (((x) >> 13) & 3) /* OBFF enabled */
912 #define PCI_EXP_DEVSTA2 0x2a /* Device Status */
913 #define PCI_EXP_LNKCAP2 0x2c /* Link Capabilities */
914 #define PCI_EXP_LNKCAP2_SPEED(x) (((x) >> 1) & 0x7f)
915 #define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink Supported */
916 #define PCI_EXP_LNKCAP2_RETIMER 0x00800000 /* Retimer Supported */
917 #define PCI_EXP_LNKCAP2_2RETIMERS 0x01000000 /* 2 Retimers Supported */
918 #define PCI_EXP_LNKCAP2_DRS 0x80000000 /* Device Readiness Status */
919 #define PCI_EXP_LNKCTL2 0x30 /* Link Control */
920 #define PCI_EXP_LNKCTL2_SPEED(x) ((x) & 0xf) /* Target Link Speed */
921 #define PCI_EXP_LNKCTL2_CMPLNC 0x0010 /* Enter Compliance */
922 #define PCI_EXP_LNKCTL2_SPEED_DIS 0x0020 /* Hardware Autonomous Speed Disable */
923 #define PCI_EXP_LNKCTL2_DEEMPHASIS(x) (((x) >> 6) & 1) /* Selectable De-emphasis */
924 #define PCI_EXP_LNKCTL2_MARGIN(x) (((x) >> 7) & 7) /* Transmit Margin */
925 #define PCI_EXP_LNKCTL2_MOD_CMPLNC 0x0400 /* Enter Modified Compliance */
926 #define PCI_EXP_LNKCTL2_CMPLNC_SOS 0x0800 /* Compliance SOS */
927 #define PCI_EXP_LNKCTL2_COM_DEEMPHASIS(x) (((x) >> 12) & 0xf) /* Compliance Preset/De-emphasis */
928 #define PCI_EXP_LNKSTA2 0x32 /* Link Status */
929 #define PCI_EXP_LINKSTA2_DEEMPHASIS(x) ((x) & 1) /* Current De-emphasis Level */
930 #define PCI_EXP_LINKSTA2_EQU_COMP 0x02 /* Equalization Complete */
931 #define PCI_EXP_LINKSTA2_EQU_PHASE1 0x04 /* Equalization Phase 1 Successful */
932 #define PCI_EXP_LINKSTA2_EQU_PHASE2 0x08 /* Equalization Phase 2 Successful */
933 #define PCI_EXP_LINKSTA2_EQU_PHASE3 0x10 /* Equalization Phase 3 Successful */
934 #define PCI_EXP_LINKSTA2_EQU_REQ 0x20 /* Link Equalization Request */
935 #define PCI_EXP_LINKSTA2_RETIMER 0x0040 /* Retimer Detected */
936 #define PCI_EXP_LINKSTA2_2RETIMERS 0x0080 /* 2 Retimers Detected */
937 #define PCI_EXP_LINKSTA2_CROSSLINK(x) (((x) >> 8) & 0x3) /* Crosslink Res */
938 #define PCI_EXP_LINKSTA2_COMPONENT(x) (((x) >> 12) & 0x7) /* Presence */
939 #define PCI_EXP_LINKSTA2_DRS_RCVD 0x8000 /* DRS Msg Received */
940 #define PCI_EXP_SLTCAP2 0x34 /* Slot Capabilities */
941 #define PCI_EXP_SLTCTL2 0x38 /* Slot Control */
942 #define PCI_EXP_SLTSTA2 0x3a /* Slot Status */
945 #define PCI_MSIX_ENABLE 0x8000
946 #define PCI_MSIX_MASK 0x4000
947 #define PCI_MSIX_TABSIZE 0x07ff
948 #define PCI_MSIX_TABLE 4
949 #define PCI_MSIX_PBA 8
950 #define PCI_MSIX_BIR 0x7
952 /* Subsystem vendor/device ID for PCI bridges */
953 #define PCI_SSVID_VENDOR 4
954 #define PCI_SSVID_DEVICE 6
956 /* PCI Advanced Features */
958 #define PCI_AF_CAP_TP 0x01
959 #define PCI_AF_CAP_FLR 0x02
960 #define PCI_AF_CTRL 4
961 #define PCI_AF_CTRL_FLR 0x01
962 #define PCI_AF_STATUS 5
963 #define PCI_AF_STATUS_TP 0x01
965 /* SATA Host Bus Adapter */
966 #define PCI_SATA_HBA_BARS 4
967 #define PCI_SATA_HBA_REG0 8
969 /* Enhanced Allocation (EA) */
970 #define PCI_EA_CAP_TYPE1_SECONDARY 4
971 #define PCI_EA_CAP_TYPE1_SUBORDINATE 5
972 /* EA Entry header */
973 #define PCI_EA_CAP_ENT_WRITABLE 0x40000000 /* Writable: 1 = RW, 0 = HwInit */
974 #define PCI_EA_CAP_ENT_ENABLE 0x80000000 /* Enable for this entry */
976 /*** Definitions of extended capabilities ***/
978 /* Advanced Error Reporting */
979 #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
980 #define PCI_ERR_UNC_TRAIN 0x00000001 /* Undefined in PCIe rev1.1 & 2.0 spec */
981 #define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
982 #define PCI_ERR_UNC_SDES 0x00000020 /* Surprise Down Error */
983 #define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
984 #define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
985 #define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
986 #define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */
987 #define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */
988 #define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */
989 #define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
990 #define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */
991 #define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */
992 #define PCI_ERR_UNC_ACS_VIOL 0x00200000 /* ACS Violation */
993 #define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */
994 /* Same bits as above */
995 #define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */
996 /* Same bits as above */
997 #define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */
998 #define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */
999 #define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */
1000 #define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
1001 #define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */
1002 #define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */
1003 #define PCI_ERR_COR_REP_ANFE 0x00002000 /* Advisory Non-Fatal Error */
1004 #define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */
1005 /* Same bits as above */
1006 #define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
1007 #define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */
1008 #define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */
1009 #define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
1010 #define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
1011 #define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
1012 #define PCI_ERR_CAP_MULT_HDRC 0x00000200 /* Multiple Header Capable */
1013 #define PCI_ERR_CAP_MULT_HDRE 0x00000400 /* Multiple Header Enable */
1014 #define PCI_ERR_CAP_TLP_PFX 0x00000800 /* TLP Prefix Log Present */
1015 #define PCI_ERR_CAP_HDR_LOG 0x00001000 /* Completion Timeout Prefix/Header Log Capable */
1016 #define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */
1017 #define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */
1018 #define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 /* Correctable Error Reporting Enable */
1019 #define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Error Reporting Enable*/
1020 #define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 /* Fatal Error Reporting Enable */
1021 #define PCI_ERR_ROOT_STATUS 48 /* Root Error Status */
1022 #define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */
1023 #define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 /* Multiple ERR_COR Received */
1024 #define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 /* ERR_FATAL/NONFATAL Received */
1025 #define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 /* Multiple ERR_FATAL/NONFATAL Received */
1026 #define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First Uncorrectable Fatal */
1027 #define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Error Messages Received */
1028 #define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Error Messages Received */
1029 #define PCI_ERR_MSG_NUM(x) (((x) >> 27) & 0x1f) /* MSI/MSI-X vector */
1030 #define PCI_ERR_ROOT_COR_SRC 52
1031 #define PCI_ERR_ROOT_SRC 54
1033 /* Virtual Channel */
1034 #define PCI_VC_PORT_REG1 4
1035 #define PCI_VC_PORT_REG2 8
1036 #define PCI_VC_PORT_CTRL 12
1037 #define PCI_VC_PORT_STATUS 14
1038 #define PCI_VC_RES_CAP 16
1039 #define PCI_VC_RES_CTRL 20
1040 #define PCI_VC_RES_STATUS 26
1042 /* Power Budgeting */
1043 #define PCI_PWR_DSR 4 /* Data Select Register */
1044 #define PCI_PWR_DATA 8 /* Data Register */
1045 #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */
1046 #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */
1047 #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */
1048 #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
1049 #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */
1050 #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
1051 #define PCI_PWR_CAP 12 /* Capability */
1052 #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
1054 /* Root Complex Link */
1055 #define PCI_RCLINK_ESD 4 /* Element Self Description */
1056 #define PCI_RCLINK_LINK1 16 /* First Link Entry */
1057 #define PCI_RCLINK_LINK_DESC 0 /* Link Entry: Description */
1058 #define PCI_RCLINK_LINK_ADDR 8 /* Link Entry: Address (64-bit) */
1059 #define PCI_RCLINK_LINK_SIZE 16 /* Link Entry: sizeof */
1061 /* Root Complex Event Collector Endpoint Association */
1062 #define PCI_RCEC_EP_CAP_VER(reg) (((reg) >> 16) & 0xf)
1063 #define PCI_RCEC_BUSN_REG_VER 0x02 /* as per PCIe sec 7.9.10.1 */
1064 #define PCI_RCEC_RCIEP_BMAP 0x0004 /* as per PCIe sec 7.9.10.2 */
1065 #define PCI_RCEC_BUSN_REG 0x0008 /* as per PCIe sec 7.9.10.3 */
1067 /* PCIe Vendor-Specific Capability */
1068 #define PCI_EVNDR_HEADER 4 /* Vendor-Specific Header */
1069 #define PCI_EVNDR_REGISTERS 8 /* Vendor-Specific Registers */
1071 /* PCIe Designated Vendor-Specific Capability */
1072 #define PCI_DVSEC_HEADER1 4 /* Designated Vendor-Specific Header 1 */
1073 #define PCI_DVSEC_HEADER2 8 /* Designated Vendor-Specific Header 2 */
1074 #define PCI_DVSEC_VENDOR_ID_CXL 0x1e98 /* Designated Vendor-Specific Vendor ID for CXL */
1075 #define PCI_DVSEC_ID_CXL 0 /* Designated Vendor-Specific ID for Intel CXL */
1077 /* PCIe CXL Designated Vendor-Specific Capabilities for Devices: Control, Status */
1078 #define PCI_CXL_DEV_LEN 0x38 /* CXL Device DVSEC Length */
1079 #define PCI_CXL_DEV_CAP 0x0a /* CXL Capability Register */
1080 #define PCI_CXL_DEV_CAP_CACHE 0x0001 /* CXL.cache Protocol Support */
1081 #define PCI_CXL_DEV_CAP_IO 0x0002 /* CXL.io Protocol Support */
1082 #define PCI_CXL_DEV_CAP_MEM 0x0004 /* CXL.mem Protocol Support */
1083 #define PCI_CXL_DEV_CAP_MEM_HWINIT 0x0008 /* CXL.mem Initializes with HW/FW Support */
1084 #define PCI_CXL_DEV_CAP_HDM_CNT(x) (((x) & (3 << 4)) >> 4) /* CXL Number of HDM ranges */
1085 #define PCI_CXL_DEV_CAP_VIRAL 0x4000 /* CXL Viral Handling Support */
1086 #define PCI_CXL_DEV_CTRL 0x0c /* CXL Control Register */
1087 #define PCI_CXL_DEV_CTRL_CACHE 0x0001 /* CXL.cache Protocol Enable */
1088 #define PCI_CXL_DEV_CTRL_IO 0x0002 /* CXL.io Protocol Enable */
1089 #define PCI_CXL_DEV_CTRL_MEM 0x0004 /* CXL.mem Protocol Enable */
1090 #define PCI_CXL_DEV_CTRL_CACHE_SF_COV(x) (((x) & (0x1f << 3)) >> 3) /* Snoop Filter Coverage */
1091 #define PCI_CXL_DEV_CTRL_CACHE_SF_GRAN(x) (((x) & (0x7 << 8)) >> 8) /* Snoop Filter Granularity */
1092 #define PCI_CXL_DEV_CTRL_CACHE_CLN 0x0800 /* CXL.cache Performance Hint on Clean Evictions */
1093 #define PCI_CXL_DEV_CTRL_VIRAL 0x4000 /* CXL Viral Handling Enable */
1094 #define PCI_CXL_DEV_STATUS 0x0e /* CXL Status Register */
1095 #define PCI_CXL_DEV_STATUS_VIRAL 0x4000 /* CXL Viral Handling Status */
1096 #define PCI_CXL_DEV_STATUS2 0x12
1097 #define PCI_CXL_DEV_STATUS_CACHE_INV 0x0001
1098 #define PCI_CXL_DEV_STATUS_RC 0x0002 /* Device Reset Complete */
1099 #define PCI_CXL_DEV_STATUS_RE 0x0004 /* Device Reset Error */
1100 #define PCI_CXL_DEV_STATUS_PMC 0x8000 /* Power Management Init Complete */
1101 #define PCI_CXL_DEV_CAP2 0x16
1102 #define PCI_CXL_DEV_CAP2_CACHE_UNK 0x0000 /* Cache Size Isn't Reported */
1103 #define PCI_CXL_DEV_CAP2_CACHE_64K 0x0001 /* Unit Size 64K */
1104 #define PCI_CXL_DEV_CAP2_CACHE_1M 0x0002 /* Unit Size 1M */
1105 #define PCI_CXL_DEV_RANGE1_SIZE_HI 0x18
1106 #define PCI_CXL_DEV_RANGE1_SIZE_LO 0x1c
1107 #define PCI_CXL_RANGE_VALID 0x0001
1108 #define PCI_CXL_RANGE_ACTIVE 0x0002
1109 #define PCI_CXL_RANGE_TYPE(x) (((x) >> 2) & 0x7)
1110 #define PCI_CXL_RANGE_CLASS(x) (((x) >> 5) & 0x7)
1111 #define PCI_CXL_RANGE_INTERLEAVE(x) (((x) >> 8) & 0x1f)
1112 #define PCI_CXL_RANGE_TIMEOUT(x) (((x) >> 13) & 0x7)
1113 #define PCI_CXL_DEV_RANGE1_BASE_HI 0x20
1114 #define PCI_CXL_DEV_RANGE1_BASE_LO 0x24
1115 #define PCI_CXL_DEV_RANGE2_SIZE_HI 0x28
1116 #define PCI_CXL_DEV_RANGE2_SIZE_LO 0x2c
1117 #define PCI_CXL_DEV_RANGE2_BASE_HI 0x30
1118 #define PCI_CXL_DEV_RANGE2_BASE_LO 0x34
1120 /* PCIe CXL 2.0 Designated Vendor-Specific Capabilities for Ports */
1121 #define PCI_CXL_PORT_EXT_LEN 0x28 /* CXL Extensions DVSEC for Ports Length */
1122 #define PCI_CXL_PORT_EXT_STATUS 0x0a /* Port Extension Status */
1123 #define PCI_CXL_PORT_PM_INIT_COMPLETE 0x1 /* Port Power Management Initialization Complete */
1124 #define PCI_CXL_PORT_CTRL 0x0c /* Port Control Override */
1125 #define PCI_CXL_PORT_UNMASK_SBR 0x0001 /* Unmask SBR */
1126 #define PCI_CXL_PORT_UNMASK_LINK 0x0002 /* Unmask Link Disable */
1127 #define PCI_CXL_PORT_ALT_MEMORY 0x0004 /* Alt Memory and ID Space Enable */
1128 #define PCI_CXL_PORT_ALT_BME 0x0008 /* Alt BME */
1129 #define PCI_CXL_PORT_VIRAL_EN 0x4000 /* Viral Enable */
1130 #define PCI_CXL_PORT_ALT_BUS_BASE 0xe
1131 #define PCI_CXL_PORT_ALT_BUS_LIMIT 0xf
1132 #define PCI_CXL_PORT_ALT_MEM_BASE 0x10
1133 #define PCI_CXL_PORT_ALT_MEM_LIMIT 0x12
1135 /* PCIe CXL 2.0 Designated Vendor-Specific Capabilities for Register Locator */
1136 #define PCI_CXL_RL_BLOCK1_LO 0x0c
1138 /* PCIe CXL Designated Vendor-Specific Capabilities for Global Persistent Flush */
1139 #define PCI_CXL_GPF_DEV_LEN 0x10
1140 #define PCI_CXL_GPF_DEV_PHASE2_DUR 0x0a /* GPF Phase 2 Duration Register */
1141 #define PCI_CXL_GPF_DEV_PHASE2_POW 0x0c /* GPF Phase 2 Power Register */
1142 #define PCI_CXL_GPF_DEV_1US 0x0
1143 #define PCI_CXL_GPF_DEV_10US 0x1
1144 #define PCI_CXL_GPF_DEV_100US 0x2
1145 #define PCI_CXL_GPF_DEV_1MS 0x3
1146 #define PCI_CXL_GPF_DEV_10MS 0x4
1147 #define PCI_CXL_GPF_DEV_100MS 0x5
1148 #define PCI_CXL_GPF_DEV_1S 0x6
1149 #define PCI_CXL_GPF_DEV_10S 0x7
1150 #define PCI_CXL_GPF_PORT_LEN 0x10
1151 #define PCI_CXL_GPF_PORT_PHASE1_CTRL 0x0c /* GPF Phase 1 Control Register */
1152 #define PCI_CXL_GPF_PORT_PHASE2_CTRL 0x0e /* GPF Phase 2 Control Register */
1153 #define PCI_CXL_GPF_PORT_1US 0x0
1154 #define PCI_CXL_GPF_PORT_10US 0x1
1155 #define PCI_CXL_GPF_PORT_100US 0x2
1156 #define PCI_CXL_GPF_PORT_1MS 0x3
1157 #define PCI_CXL_GPF_PORT_10MS 0x4
1158 #define PCI_CXL_GPF_PORT_100MS 0x5
1159 #define PCI_CXL_GPF_PORT_1S 0x6
1160 #define PCI_CXL_GPF_PORT_10S 0x7
1162 /* PCIe CXL Designated Vendor-Specific Capabilities for Flex Bus Port */
1163 #define PCI_CXL_FB_LEN 0x20
1164 #define PCI_CXL_FB_PORT_CAP 0x0a /* CXL Flex Bus Port Capability Register */
1165 #define PCI_CXL_FB_CAP_CACHE 0x0001 /* CXL.cache Capable */
1166 #define PCI_CXL_FB_CAP_IO 0x0002 /* CXL.io Capable */
1167 #define PCI_CXL_FB_CAP_MEM 0x0004 /* CXL.mem Capable */
1168 #define PCI_CXL_FB_CAP_68B_FLIT 0x0020 /* CXL 68B Flit and VH Capable */
1169 #define PCI_CXL_FB_CAP_MULT_LOG_DEV 0x0040 /* CXL Multi-Logical Device Capable */
1170 #define PCI_CXL_FB_CAP_256B_FLIT 0x2000 /* CXL Latency Optimized 256B Flit Capable */
1171 #define PCI_CXL_FB_CAP_PBR_FLIT 0x4000 /* CXL PBR Flit Capable */
1172 #define PCI_CXL_FB_PORT_CTRL 0x0c /* CXL Flex Bus Port Control Register */
1173 #define PCI_CXL_FB_CTRL_CACHE 0x0001 /* CXL.cache Enable */
1174 #define PCI_CXL_FB_CTRL_IO 0x0002 /* CXL.io Enable */
1175 #define PCI_CXL_FB_CTRL_MEM 0x0004 /* CXL.mem Enable */
1176 #define PCI_CXL_FB_CTRL_SYNC_HDR_BYP 0x0008 /* CXL Sync Header Bypass Enable */
1177 #define PCI_CXL_FB_CTRL_DRFT_BUF 0x0010 /* Drift Buffer Enable */
1178 #define PCI_CXL_FB_CTRL_68B_FLIT 0x0020 /* CXL 68B Flit and VH Enable */
1179 #define PCI_CXL_FB_CTRL_MULT_LOG_DEV 0x0040 /* CXL Multi Logical Device Enable */
1180 #define PCI_CXL_FB_CTRL_RCD 0x0080 /* Disable RCD Training */
1181 #define PCI_CXL_FB_CTRL_RETIMER1 0x0100 /* Retimer1 Present */
1182 #define PCI_CXL_FB_CTRL_RETIMER2 0x0200 /* Retimer2 Present */
1183 #define PCI_CXL_FB_CTRL_256B_FLIT 0x2000 /* CXL Latency Optimized 256B Flit Enable */
1184 #define PCI_CXL_FB_CTRL_PBR_FLIT 0x4000 /* CXL PBR Flit Enable */
1185 #define PCI_CXL_FB_PORT_STATUS 0x0e /* CXL Flex Bus Port Status Register */
1186 #define PCI_CXL_FB_STAT_CACHE 0x0001 /* CXL.cache Enabled */
1187 #define PCI_CXL_FB_STAT_IO 0x0002 /* CXL.io Enabled */
1188 #define PCI_CXL_FB_STAT_MEM 0x0004 /* CXL.mem Enabled */
1189 #define PCI_CXL_FB_STAT_SYNC_HDR_BYP 0x0008 /* CXL Sync Header Bypass Enabled */
1190 #define PCI_CXL_FB_STAT_DRFT_BUF 0x0010 /* Drift Buffer Enabled */
1191 #define PCI_CXL_FB_STAT_68B_FLIT 0x0020 /* CXL 68B Flit and VH Enabled */
1192 #define PCI_CXL_FB_STAT_MULT_LOG_DEV 0x0040 /* CXL Multi Logical Device Enabled */
1193 #define PCI_CXL_FB_STAT_256B_FLIT 0x2000 /* CXL Latency Optimized 256B Flit Enabled */
1194 #define PCI_CXL_FB_STAT_PBR_FLIT 0x4000 /* CXL PBR Flit Enabled */
1195 #define PCI_CXL_FB_MOD_TS_DATA 0x10 /* CXL Flex Bus Port Received Modified TS Data Phase1 Register */
1196 #define PCI_CXL_FB_PORT_CAP2 0x14 /* CXL Flex Bus Port Capability2 Register */
1197 #define PCI_CXL_FB_CAP2_NOP_HINT 0x01 /* NOP Hint Capable */
1198 #define PCI_CXL_FB_PORT_CTRL2 0x18 /* CXL Flex Bus Port Control2 Register */
1199 #define PCI_CXL_FB_CTRL2_NOP_HINT 0x01 /* NOP Hint Enable */
1200 #define PCI_CXL_FB_PORT_STATUS2 0x1c /* CXL Flex Bus Port Status2 Register */
1202 /* PCIe CXL Designated Vendor-Specific Capabilities for Multi-Logical Device */
1203 #define PCI_CXL_MLD_LEN 0x10
1204 #define PCI_CXL_MLD_NUM_LD 0xa
1205 #define PCI_CXL_MLD_MAX_LD 0x10
1207 /* PCIe CXL Designated Vendor-Specific Capabilities for Non-CXL Function Map */
1208 #define PCI_CXL_FUN_MAP_LEN 0x2c
1209 #define PCI_CXL_FUN_MAP_REG_0 0x0c
1210 #define PCI_CXL_FUN_MAP_REG_1 0x10
1211 #define PCI_CXL_FUN_MAP_REG_2 0x14
1212 #define PCI_CXL_FUN_MAP_REG_3 0x18
1213 #define PCI_CXL_FUN_MAP_REG_4 0x1c
1214 #define PCI_CXL_FUN_MAP_REG_5 0x20
1215 #define PCI_CXL_FUN_MAP_REG_6 0x24
1216 #define PCI_CXL_FUN_MAP_REG_7 0x28
1218 /* Access Control Services */
1219 #define PCI_ACS_CAP 0x04 /* ACS Capability Register */
1220 #define PCI_ACS_CAP_VALID 0x0001 /* ACS Source Validation */
1221 #define PCI_ACS_CAP_BLOCK 0x0002 /* ACS Translation Blocking */
1222 #define PCI_ACS_CAP_REQ_RED 0x0004 /* ACS P2P Request Redirect */
1223 #define PCI_ACS_CAP_CMPLT_RED 0x0008 /* ACS P2P Completion Redirect */
1224 #define PCI_ACS_CAP_FORWARD 0x0010 /* ACS Upstream Forwarding */
1225 #define PCI_ACS_CAP_EGRESS 0x0020 /* ACS P2P Egress Control */
1226 #define PCI_ACS_CAP_TRANS 0x0040 /* ACS Direct Translated P2P */
1227 #define PCI_ACS_CAP_VECTOR(x) (((x) >> 8) & 0xff) /* Egress Control Vector Size */
1228 #define PCI_ACS_CTRL 0x06 /* ACS Control Register */
1229 #define PCI_ACS_CTRL_VALID 0x0001 /* ACS Source Validation Enable */
1230 #define PCI_ACS_CTRL_BLOCK 0x0002 /* ACS Translation Blocking Enable */
1231 #define PCI_ACS_CTRL_REQ_RED 0x0004 /* ACS P2P Request Redirect Enable */
1232 #define PCI_ACS_CTRL_CMPLT_RED 0x0008 /* ACS P2P Completion Redirect Enable */
1233 #define PCI_ACS_CTRL_FORWARD 0x0010 /* ACS Upstream Forwarding Enable */
1234 #define PCI_ACS_CTRL_EGRESS 0x0020 /* ACS P2P Egress Control Enable */
1235 #define PCI_ACS_CTRL_TRANS 0x0040 /* ACS Direct Translated P2P Enable */
1236 #define PCI_ACS_EGRESS_CTRL 0x08 /* Egress Control Vector */
1238 /* Alternative Routing-ID Interpretation */
1239 #define PCI_ARI_CAP 0x04 /* ARI Capability Register */
1240 #define PCI_ARI_CAP_MFVC 0x0001 /* MFVC Function Groups Capability */
1241 #define PCI_ARI_CAP_ACS 0x0002 /* ACS Function Groups Capability */
1242 #define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */
1243 #define PCI_ARI_CTRL 0x06 /* ARI Control Register */
1244 #define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */
1245 #define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */
1246 #define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */
1248 /* Address Translation Service */
1249 #define PCI_ATS_CAP 0x04 /* ATS Capability Register */
1250 #define PCI_ATS_CAP_IQD(x) ((x) & 0x1f) /* Invalidate Queue Depth */
1251 #define PCI_ATS_CTRL 0x06 /* ATS Control Register */
1252 #define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */
1253 #define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */
1255 /* Single Root I/O Virtualization */
1256 #define PCI_IOV_CAP 0x04 /* SR-IOV Capability Register */
1257 #define PCI_IOV_CAP_VFM 0x00000001 /* VF Migration Capable */
1258 #define PCI_IOV_CAP_VF_10BIT_TAG_REQ 0x00000004 /* VF 10-Bit Tag Requester Supported */
1259 #define PCI_IOV_CAP_IMN(x) ((x) >> 21) /* VF Migration Interrupt Message Number */
1260 #define PCI_IOV_CTRL 0x08 /* SR-IOV Control Register */
1261 #define PCI_IOV_CTRL_VFE 0x0001 /* VF Enable */
1262 #define PCI_IOV_CTRL_VFME 0x0002 /* VF Migration Enable */
1263 #define PCI_IOV_CTRL_VFMIE 0x0004 /* VF Migration Interrupt Enable */
1264 #define PCI_IOV_CTRL_MSE 0x0008 /* VF MSE */
1265 #define PCI_IOV_CTRL_ARI 0x0010 /* ARI Capable Hierarchy */
1266 #define PCI_IOV_CTRL_VF_10BIT_TAG_REQ_EN 0x0020 /* VF 10-Bit Tag Requester Enable */
1267 #define PCI_IOV_STATUS 0x0a /* SR-IOV Status Register */
1268 #define PCI_IOV_STATUS_MS 0x0001 /* VF Migration Status */
1269 #define PCI_IOV_INITIALVF 0x0c /* Number of VFs that are initially associated */
1270 #define PCI_IOV_TOTALVF 0x0e /* Maximum number of VFs that could be associated */
1271 #define PCI_IOV_NUMVF 0x10 /* Number of VFs that are available */
1272 #define PCI_IOV_FDL 0x12 /* Function Dependency Link */
1273 #define PCI_IOV_OFFSET 0x14 /* First VF Offset */
1274 #define PCI_IOV_STRIDE 0x16 /* Routing ID offset from one VF to the next one */
1275 #define PCI_IOV_DID 0x1a /* VF Device ID */
1276 #define PCI_IOV_SUPPS 0x1c /* Supported Page Sizes */
1277 #define PCI_IOV_SYSPS 0x20 /* System Page Size */
1278 #define PCI_IOV_BAR_BASE 0x24 /* VF BAR0, VF BAR1, ... VF BAR5 */
1279 #define PCI_IOV_NUM_BAR 6 /* Number of VF BARs */
1280 #define PCI_IOV_MSAO 0x3c /* VF Migration State Array Offset */
1281 #define PCI_IOV_MSA_BIR(x) ((x) & 7) /* VF Migration State BIR */
1282 #define PCI_IOV_MSA_OFFSET(x) ((x) & 0xfffffff8) /* VF Migration State Offset */
1285 #define PCI_MCAST_CAP 0x04 /* Multicast Capability */
1286 #define PCI_MCAST_CAP_MAX_GROUP(x) ((x) & 0x3f)
1287 #define PCI_MCAST_CAP_WIN_SIZE(x) (((x) >> 8) & 0x3f)
1288 #define PCI_MCAST_CAP_ECRC 0x8000 /* ECRC Regeneration Supported */
1289 #define PCI_MCAST_CTRL 0x06 /* Multicast Control */
1290 #define PCI_MCAST_CTRL_NUM_GROUP(x) ((x) & 0x3f)
1291 #define PCI_MCAST_CTRL_ENABLE 0x8000 /* MC Enabled */
1292 #define PCI_MCAST_BAR 0x08 /* Base Address */
1293 #define PCI_MCAST_BAR_INDEX_POS(x) ((u32) ((x) & 0x3f))
1294 #define PCI_MCAST_BAR_MASK (~0xfffUL)
1295 #define PCI_MCAST_RCV 0x10 /* Receive */
1296 #define PCI_MCAST_BLOCK 0x18 /* Block All */
1297 #define PCI_MCAST_BLOCK_UNTRANS 0x20 /* Block Untranslated */
1298 #define PCI_MCAST_OVL_BAR 0x28 /* Overlay BAR */
1299 #define PCI_MCAST_OVL_SIZE(x) ((u32) ((x) & 0x3f))
1300 #define PCI_MCAST_OVL_MASK (~0x3fUL)
1302 /* Page Request Interface */
1303 #define PCI_PRI_CTRL 0x04 /* PRI Control Register */
1304 #define PCI_PRI_CTRL_ENABLE 0x01 /* Enable */
1305 #define PCI_PRI_CTRL_RESET 0x02 /* Reset */
1306 #define PCI_PRI_STATUS 0x06 /* PRI status register */
1307 #define PCI_PRI_STATUS_RF 0x001 /* Response Failure */
1308 #define PCI_PRI_STATUS_UPRGI 0x002 /* Unexpected PRG index */
1309 #define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */
1310 #define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */
1311 #define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */
1313 /* Transaction Processing Hints */
1314 #define PCI_TPH_CAPABILITIES 4
1315 #define PCI_TPH_INTVEC_SUP (1<<1) /* Supports interrupt vector mode */
1316 #define PCI_TPH_DEV_SUP (1<<2) /* Device specific mode supported */
1317 #define PCI_TPH_EXT_REQ_SUP (1<<8) /* Supports extended requests */
1318 #define PCI_TPH_ST_LOC_MASK (3<<9) /* Steering table location bits */
1319 #define PCI_TPH_ST_NONE (0<<9) /* No steering table */
1320 #define PCI_TPH_ST_CAP (1<<9) /* Steering table in TPH cap */
1321 #define PCI_TPH_ST_MSIX (2<<9) /* Steering table in MSI-X table */
1322 #define PCI_TPH_ST_SIZE_SHIFT (16) /* Encoded as size - 1 */
1324 /* Latency Tolerance Reporting */
1325 #define PCI_LTR_MAX_SNOOP 4 /* 16 bit value */
1326 #define PCI_LTR_VALUE_MASK (0x3ff)
1327 #define PCI_LTR_SCALE_SHIFT (10)
1328 #define PCI_LTR_SCALE_MASK (7)
1329 #define PCI_LTR_MAX_NOSNOOP 6 /* 16 bit value */
1331 /* Secondary PCI Express Extended Capability */
1332 #define PCI_SEC_LNKCTL3 4 /* Link Control 3 register */
1333 #define PCI_SEC_LNKCTL3_PERFORM_LINK_EQU 0x01
1334 #define PCI_SEC_LNKCTL3_LNK_EQU_REQ_INTR_EN 0x02
1335 #define PCI_SEC_LNKCTL3_ENBL_LOWER_SKP_OS_GEN_VEC(x) ((x >> 8) & 0x7F)
1336 #define PCI_SEC_LANE_ERR 8 /* Lane Error status register */
1337 #define PCI_SEC_LANE_EQU_CTRL 12 /* Lane Equalization control register */
1339 /* Process Address Space ID */
1340 #define PCI_PASID_CAP 0x04 /* PASID feature register */
1341 #define PCI_PASID_CAP_EXEC 0x02 /* Exec permissions Supported */
1342 #define PCI_PASID_CAP_PRIV 0x04 /* Privilege Mode Supported */
1343 #define PCI_PASID_CAP_WIDTH(x) (((x) >> 8) & 0x1f) /* Max PASID Width */
1344 #define PCI_PASID_CTRL 0x06 /* PASID control register */
1345 #define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */
1346 #define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */
1347 #define PCI_PASID_CTRL_PRIV 0x04 /* Privilege Mode Enable */
1349 #define PCI_DPC_CAP 4 /* DPC Capability */
1350 #define PCI_DPC_CAP_INT_MSG(x) ((x) & 0x1f) /* DPC Interrupt Message Number */
1351 #define PCI_DPC_CAP_RP_EXT 0x20 /* DPC Root Port Extensions */
1352 #define PCI_DPC_CAP_TLP_BLOCK 0x40 /* DPC Poisoned TLP Egress Blocking */
1353 #define PCI_DPC_CAP_SW_TRIGGER 0x80 /* DPC Software Trigger */
1354 #define PCI_DPC_CAP_RP_LOG(x) (((x) >> 8) & 0xf) /* DPC RP PIO Log Size */
1355 #define PCI_DPC_CAP_DL_ACT_ERR 0x1000 /* DPC DL_Active ERR_COR Signal */
1356 #define PCI_DPC_CTL 6 /* DPC Control */
1357 #define PCI_DPC_CTL_TRIGGER(x) ((x) & 0x3) /* DPC Trigger Enable */
1358 #define PCI_DPC_CTL_CMPL 0x4 /* DPC Completion Control */
1359 #define PCI_DPC_CTL_INT 0x8 /* DPC Interrupt Enabled */
1360 #define PCI_DPC_CTL_ERR_COR 0x10 /* DPC ERR_COR Enabled */
1361 #define PCI_DPC_CTL_TLP 0x20 /* DPC Poisoned TLP Egress Blocking Enabled */
1362 #define PCI_DPC_CTL_SW_TRIGGER 0x40 /* DPC Software Trigger */
1363 #define PCI_DPC_CTL_DL_ACTIVE 0x80 /* DPC DL_Active ERR_COR Enable */
1364 #define PCI_DPC_STATUS 8 /* DPC STATUS */
1365 #define PCI_DPC_STS_TRIGGER 0x01 /* DPC Trigger Status */
1366 #define PCI_DPC_STS_REASON(x) (((x) >> 1) & 0x3) /* DPC Trigger Reason */
1367 #define PCI_DPC_STS_INT 0x08 /* DPC Interrupt Status */
1368 #define PCI_DPC_STS_RP_BUSY 0x10 /* DPC Root Port Busy */
1369 #define PCI_DPC_STS_TRIGGER_EXT(x) (((x) >> 5) & 0x3) /* Trigger Reason Extension */
1370 #define PCI_DPC_STS_PIO_FEP(x) (((x) >> 8) & 0x1f) /* DPC PIO First Error Pointer */
1371 #define PCI_DPC_SOURCE 10 /* DPC Source ID */
1373 /* L1 PM Substates Extended Capability */
1374 #define PCI_L1PM_SUBSTAT_CAP 0x4 /* L1 PM Substate Capability */
1375 #define PCI_L1PM_SUBSTAT_CAP_PM_L12 0x1 /* PCI-PM L1.2 Supported */
1376 #define PCI_L1PM_SUBSTAT_CAP_PM_L11 0x2 /* PCI-PM L1.1 Supported */
1377 #define PCI_L1PM_SUBSTAT_CAP_ASPM_L12 0x4 /* ASPM L1.2 Supported */
1378 #define PCI_L1PM_SUBSTAT_CAP_ASPM_L11 0x8 /* ASPM L1.1 Supported */
1379 #define PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP 0x10 /* L1 PM Substates supported */
1380 #define PCI_L1PM_SUBSTAT_CTL1 0x8 /* L1 PM Substate Control 1 */
1381 #define PCI_L1PM_SUBSTAT_CTL1_PM_L12 0x1 /* PCI-PM L1.2 Enable */
1382 #define PCI_L1PM_SUBSTAT_CTL1_PM_L11 0x2 /* PCI-PM L1.1 Enable */
1383 #define PCI_L1PM_SUBSTAT_CTL1_ASPM_L12 0x4 /* ASPM L1.2 Enable */
1384 #define PCI_L1PM_SUBSTAT_CTL1_ASPM_L11 0x8 /* ASPM L1.1 Enable */
1385 #define PCI_L1PM_SUBSTAT_CTL2 0xC /* L1 PM Substate Control 2 */
1387 /* Data Object Exchange Extended Capability */
1388 #define PCI_DOE_CAP 0x4 /* DOE Capabilities Register */
1389 #define PCI_DOE_CAP_INT_SUPP 0x1 /* Interrupt Support */
1390 #define PCI_DOE_CAP_INT_MSG(x) (((x) >> 1) & 0x7ff) /* DOE Interrupt Message Number */
1391 #define PCI_DOE_CTL 0x8 /* DOE Control Register */
1392 #define PCI_DOE_CTL_ABORT 0x1 /* DOE Abort */
1393 #define PCI_DOE_CTL_INT 0x2 /* DOE Interrupt Enable */
1394 #define PCI_DOE_CTL_GO 0x80000000 /* DOE Go */
1395 #define PCI_DOE_STS 0xC /* DOE Status Register */
1396 #define PCI_DOE_STS_BUSY 0x1 /* DOE Busy */
1397 #define PCI_DOE_STS_INT 0x2 /* DOE Interrupt Status */
1398 #define PCI_DOE_STS_ERROR 0x4 /* DOE Error */
1399 #define PCI_DOE_STS_OBJECT_READY 0x80000000 /* Data Object Ready */
1402 * The PCI interface treats multi-function devices as independent
1403 * devices. The slot/function address of each device is encoded
1404 * in a single byte as follows:
1409 #define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
1410 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
1411 #define PCI_FUNC(devfn) ((devfn) & 0x07)
1413 /* Device classes and subclasses */
1415 #define PCI_CLASS_NOT_DEFINED 0x0000
1416 #define PCI_CLASS_NOT_DEFINED_VGA 0x0001
1418 #define PCI_BASE_CLASS_STORAGE 0x01
1419 #define PCI_CLASS_STORAGE_SCSI 0x0100
1420 #define PCI_CLASS_STORAGE_IDE 0x0101
1421 #define PCI_CLASS_STORAGE_FLOPPY 0x0102
1422 #define PCI_CLASS_STORAGE_IPI 0x0103
1423 #define PCI_CLASS_STORAGE_RAID 0x0104
1424 #define PCI_CLASS_STORAGE_ATA 0x0105
1425 #define PCI_CLASS_STORAGE_SATA 0x0106
1426 #define PCI_CLASS_STORAGE_SAS 0x0107
1427 #define PCI_CLASS_STORAGE_OTHER 0x0180
1429 #define PCI_BASE_CLASS_NETWORK 0x02
1430 #define PCI_CLASS_NETWORK_ETHERNET 0x0200
1431 #define PCI_CLASS_NETWORK_TOKEN_RING 0x0201
1432 #define PCI_CLASS_NETWORK_FDDI 0x0202
1433 #define PCI_CLASS_NETWORK_ATM 0x0203
1434 #define PCI_CLASS_NETWORK_ISDN 0x0204
1435 #define PCI_CLASS_NETWORK_OTHER 0x0280
1437 #define PCI_BASE_CLASS_DISPLAY 0x03
1438 #define PCI_CLASS_DISPLAY_VGA 0x0300
1439 #define PCI_CLASS_DISPLAY_XGA 0x0301
1440 #define PCI_CLASS_DISPLAY_3D 0x0302
1441 #define PCI_CLASS_DISPLAY_OTHER 0x0380
1443 #define PCI_BASE_CLASS_MULTIMEDIA 0x04
1444 #define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400
1445 #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401
1446 #define PCI_CLASS_MULTIMEDIA_PHONE 0x0402
1447 #define PCI_CLASS_MULTIMEDIA_AUDIO_DEV 0x0403
1448 #define PCI_CLASS_MULTIMEDIA_OTHER 0x0480
1450 #define PCI_BASE_CLASS_MEMORY 0x05
1451 #define PCI_CLASS_MEMORY_RAM 0x0500
1452 #define PCI_CLASS_MEMORY_FLASH 0x0501
1453 #define PCI_CLASS_MEMORY_OTHER 0x0580
1455 #define PCI_BASE_CLASS_BRIDGE 0x06
1456 #define PCI_CLASS_BRIDGE_HOST 0x0600
1457 #define PCI_CLASS_BRIDGE_ISA 0x0601
1458 #define PCI_CLASS_BRIDGE_EISA 0x0602
1459 #define PCI_CLASS_BRIDGE_MC 0x0603
1460 #define PCI_CLASS_BRIDGE_PCI 0x0604
1461 #define PCI_CLASS_BRIDGE_PCMCIA 0x0605
1462 #define PCI_CLASS_BRIDGE_NUBUS 0x0606
1463 #define PCI_CLASS_BRIDGE_CARDBUS 0x0607
1464 #define PCI_CLASS_BRIDGE_RACEWAY 0x0608
1465 #define PCI_CLASS_BRIDGE_PCI_SEMI 0x0609
1466 #define PCI_CLASS_BRIDGE_IB_TO_PCI 0x060a
1467 #define PCI_CLASS_BRIDGE_OTHER 0x0680
1469 #define PCI_BASE_CLASS_COMMUNICATION 0x07
1470 #define PCI_CLASS_COMMUNICATION_SERIAL 0x0700
1471 #define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
1472 #define PCI_CLASS_COMMUNICATION_MSERIAL 0x0702
1473 #define PCI_CLASS_COMMUNICATION_MODEM 0x0703
1474 #define PCI_CLASS_COMMUNICATION_OTHER 0x0780
1476 #define PCI_BASE_CLASS_SYSTEM 0x08
1477 #define PCI_CLASS_SYSTEM_PIC 0x0800
1478 #define PCI_CLASS_SYSTEM_DMA 0x0801
1479 #define PCI_CLASS_SYSTEM_TIMER 0x0802
1480 #define PCI_CLASS_SYSTEM_RTC 0x0803
1481 #define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804
1482 #define PCI_CLASS_SYSTEM_OTHER 0x0880
1484 #define PCI_BASE_CLASS_INPUT 0x09
1485 #define PCI_CLASS_INPUT_KEYBOARD 0x0900
1486 #define PCI_CLASS_INPUT_PEN 0x0901
1487 #define PCI_CLASS_INPUT_MOUSE 0x0902
1488 #define PCI_CLASS_INPUT_SCANNER 0x0903
1489 #define PCI_CLASS_INPUT_GAMEPORT 0x0904
1490 #define PCI_CLASS_INPUT_OTHER 0x0980
1492 #define PCI_BASE_CLASS_DOCKING 0x0a
1493 #define PCI_CLASS_DOCKING_GENERIC 0x0a00
1494 #define PCI_CLASS_DOCKING_OTHER 0x0a80
1496 #define PCI_BASE_CLASS_PROCESSOR 0x0b
1497 #define PCI_CLASS_PROCESSOR_386 0x0b00
1498 #define PCI_CLASS_PROCESSOR_486 0x0b01
1499 #define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02
1500 #define PCI_CLASS_PROCESSOR_ALPHA 0x0b10
1501 #define PCI_CLASS_PROCESSOR_POWERPC 0x0b20
1502 #define PCI_CLASS_PROCESSOR_MIPS 0x0b30
1503 #define PCI_CLASS_PROCESSOR_CO 0x0b40
1505 #define PCI_BASE_CLASS_SERIAL 0x0c
1506 #define PCI_CLASS_SERIAL_FIREWIRE 0x0c00
1507 #define PCI_CLASS_SERIAL_ACCESS 0x0c01
1508 #define PCI_CLASS_SERIAL_SSA 0x0c02
1509 #define PCI_CLASS_SERIAL_USB 0x0c03
1510 #define PCI_CLASS_SERIAL_FIBER 0x0c04
1511 #define PCI_CLASS_SERIAL_SMBUS 0x0c05
1512 #define PCI_CLASS_SERIAL_INFINIBAND 0x0c06
1514 #define PCI_BASE_CLASS_WIRELESS 0x0d
1515 #define PCI_CLASS_WIRELESS_IRDA 0x0d00
1516 #define PCI_CLASS_WIRELESS_CONSUMER_IR 0x0d01
1517 #define PCI_CLASS_WIRELESS_RF 0x0d10
1518 #define PCI_CLASS_WIRELESS_OTHER 0x0d80
1520 #define PCI_BASE_CLASS_INTELLIGENT 0x0e
1521 #define PCI_CLASS_INTELLIGENT_I2O 0x0e00
1523 #define PCI_BASE_CLASS_SATELLITE 0x0f
1524 #define PCI_CLASS_SATELLITE_TV 0x0f00
1525 #define PCI_CLASS_SATELLITE_AUDIO 0x0f01
1526 #define PCI_CLASS_SATELLITE_VOICE 0x0f03
1527 #define PCI_CLASS_SATELLITE_DATA 0x0f04
1529 #define PCI_BASE_CLASS_CRYPT 0x10
1530 #define PCI_CLASS_CRYPT_NETWORK 0x1000
1531 #define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1010
1532 #define PCI_CLASS_CRYPT_OTHER 0x1080
1534 #define PCI_BASE_CLASS_SIGNAL 0x11
1535 #define PCI_CLASS_SIGNAL_DPIO 0x1100
1536 #define PCI_CLASS_SIGNAL_PERF_CTR 0x1101
1537 #define PCI_CLASS_SIGNAL_SYNCHRONIZER 0x1110
1538 #define PCI_CLASS_SIGNAL_OTHER 0x1180
1540 #define PCI_CLASS_OTHERS 0xff
1542 /* Several ID's we need in the library */
1544 #define PCI_VENDOR_ID_INTEL 0x8086
1545 #define PCI_VENDOR_ID_COMPAQ 0x0e11
1547 /* I/O resource flags, compatible with <include/linux/ioport.h> */
1549 #define PCI_IORESOURCE_TYPE_BITS 0x00001f00
1550 #define PCI_IORESOURCE_IO 0x00000100
1551 #define PCI_IORESOURCE_MEM 0x00000200
1552 #define PCI_IORESOURCE_PREFETCH 0x00002000
1553 #define PCI_IORESOURCE_MEM_64 0x00100000
1554 #define PCI_IORESOURCE_IO_16BIT_ADDR (1<<0)
1555 #define PCI_IORESOURCE_PCI_EA_BEI (1<<5)