2 * $Id: header.h,v 1.9 2002/12/26 20:24:50 mj Exp $
4 * The PCI Library -- PCI Header Structure (extracted from <linux/pci.h>)
6 * Copyright (c) 1997--2002 Martin Mares <mj@ucw.cz>
8 * Can be freely distributed and used under the terms of the GNU GPL.
12 * Under PCI, each device has 256 bytes of configuration address space,
13 * of which the first 64 bytes are standardized as follows:
15 #define PCI_VENDOR_ID 0x00 /* 16 bits */
16 #define PCI_DEVICE_ID 0x02 /* 16 bits */
17 #define PCI_COMMAND 0x04 /* 16 bits */
18 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
19 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
20 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
21 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
22 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
23 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
24 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
25 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
26 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
27 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
29 #define PCI_STATUS 0x06 /* 16 bits */
30 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
31 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
32 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
33 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
34 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
35 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
36 #define PCI_STATUS_DEVSEL_FAST 0x000
37 #define PCI_STATUS_DEVSEL_MEDIUM 0x200
38 #define PCI_STATUS_DEVSEL_SLOW 0x400
39 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
40 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
41 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
42 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
43 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
45 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
47 #define PCI_REVISION_ID 0x08 /* Revision ID */
48 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
49 #define PCI_CLASS_DEVICE 0x0a /* Device class */
51 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
52 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
53 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
54 #define PCI_HEADER_TYPE_NORMAL 0
55 #define PCI_HEADER_TYPE_BRIDGE 1
56 #define PCI_HEADER_TYPE_CARDBUS 2
58 #define PCI_BIST 0x0f /* 8 bits */
59 #define PCI_BIST_CODE_MASK 0x0f /* Return result */
60 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
61 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
64 * Base addresses specify locations in memory or I/O space.
65 * Decoded size can be determined by writing a value of
66 * 0xffffffff to the register, and reading it back. Only
69 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
70 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
71 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
72 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
73 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
74 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
75 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
76 #define PCI_BASE_ADDRESS_SPACE_IO 0x01
77 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
78 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
79 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
80 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
81 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
82 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
83 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
84 #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
85 /* bit 1 is reserved if address_space = 1 */
87 /* Header type 0 (normal devices) */
88 #define PCI_CARDBUS_CIS 0x28
89 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
90 #define PCI_SUBSYSTEM_ID 0x2e
91 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
92 #define PCI_ROM_ADDRESS_ENABLE 0x01
93 #define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
95 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
97 /* 0x35-0x3b are reserved */
98 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
99 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
100 #define PCI_MIN_GNT 0x3e /* 8 bits */
101 #define PCI_MAX_LAT 0x3f /* 8 bits */
103 /* Header type 1 (PCI-to-PCI bridges) */
104 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
105 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
106 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
107 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
108 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
109 #define PCI_IO_LIMIT 0x1d
110 #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
111 #define PCI_IO_RANGE_TYPE_16 0x00
112 #define PCI_IO_RANGE_TYPE_32 0x01
113 #define PCI_IO_RANGE_MASK ~0x0f
114 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
115 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */
116 #define PCI_MEMORY_LIMIT 0x22
117 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
118 #define PCI_MEMORY_RANGE_MASK ~0x0f
119 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
120 #define PCI_PREF_MEMORY_LIMIT 0x26
121 #define PCI_PREF_RANGE_TYPE_MASK 0x0f
122 #define PCI_PREF_RANGE_TYPE_32 0x00
123 #define PCI_PREF_RANGE_TYPE_64 0x01
124 #define PCI_PREF_RANGE_MASK ~0x0f
125 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
126 #define PCI_PREF_LIMIT_UPPER32 0x2c
127 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
128 #define PCI_IO_LIMIT_UPPER16 0x32
129 /* 0x34 same as for htype 0 */
130 /* 0x35-0x3b is reserved */
131 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
132 /* 0x3c-0x3d are same as for htype 0 */
133 #define PCI_BRIDGE_CONTROL 0x3e
134 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
135 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
136 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
137 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
138 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
139 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
140 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
142 /* Header type 2 (CardBus bridges) */
143 /* 0x14-0x15 reserved */
144 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
145 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
146 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
147 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
148 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
149 #define PCI_CB_MEMORY_BASE_0 0x1c
150 #define PCI_CB_MEMORY_LIMIT_0 0x20
151 #define PCI_CB_MEMORY_BASE_1 0x24
152 #define PCI_CB_MEMORY_LIMIT_1 0x28
153 #define PCI_CB_IO_BASE_0 0x2c
154 #define PCI_CB_IO_BASE_0_HI 0x2e
155 #define PCI_CB_IO_LIMIT_0 0x30
156 #define PCI_CB_IO_LIMIT_0_HI 0x32
157 #define PCI_CB_IO_BASE_1 0x34
158 #define PCI_CB_IO_BASE_1_HI 0x36
159 #define PCI_CB_IO_LIMIT_1 0x38
160 #define PCI_CB_IO_LIMIT_1_HI 0x3a
161 #define PCI_CB_IO_RANGE_MASK ~0x03
162 /* 0x3c-0x3d are same as for htype 0 */
163 #define PCI_CB_BRIDGE_CONTROL 0x3e
164 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
165 #define PCI_CB_BRIDGE_CTL_SERR 0x02
166 #define PCI_CB_BRIDGE_CTL_ISA 0x04
167 #define PCI_CB_BRIDGE_CTL_VGA 0x08
168 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
169 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
170 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
171 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
172 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
173 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
174 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
175 #define PCI_CB_SUBSYSTEM_ID 0x42
176 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
177 /* 0x48-0x7f reserved */
179 /* Capability lists */
181 #define PCI_CAP_LIST_ID 0 /* Capability ID */
182 #define PCI_CAP_ID_PM 0x01 /* Power Management */
183 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
184 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
185 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
186 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
187 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
188 #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
189 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
190 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
191 #define PCI_CAP_SIZEOF 4
193 /* Power Management Registers */
195 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version (2=PM1.1) */
196 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* Clock required for PME generation */
197 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization required */
198 #define PCI_PM_CAP_AUX_C_MASK 0x01c0 /* Maximum aux current required in D3cold */
199 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
200 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
201 #define PCI_PM_CAP_PME_D0 0x0800 /* PME can be asserted from D0 */
202 #define PCI_PM_CAP_PME_D1 0x1000 /* PME can be asserted from D1 */
203 #define PCI_PM_CAP_PME_D2 0x2000 /* PME can be asserted from D2 */
204 #define PCI_PM_CAP_PME_D3_HOT 0x4000 /* PME can be asserted from D3hot */
205 #define PCI_PM_CAP_PME_D3_COLD 0x8000 /* PME can be asserted from D3cold */
206 #define PCI_PM_CTRL 4 /* PM control and status register */
207 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
208 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
209 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* PM table data index */
210 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* PM table data scaling factor */
211 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
212 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions */
213 #define PCI_PM_PPB_B2_B3 0x40 /* If bridge enters D3hot, bus enters: 0=B3, 1=B2 */
214 #define PCI_PM_BPCC_ENABLE 0x80 /* Secondary bus is power managed */
215 #define PCI_PM_DATA_REGISTER 7 /* PM table contents read here */
216 #define PCI_PM_SIZEOF 8
220 #define PCI_AGP_VERSION 2 /* BCD version number */
221 #define PCI_AGP_RFU 3 /* Rest of capability flags */
222 #define PCI_AGP_STATUS 4 /* Status register */
223 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
224 #define PCI_AGP_STATUS_ISOCH 0x10000 /* Isochronous transactions supported */
225 #define PCI_AGP_STATUS_ARQSZ_MASK 0xe000 /* log2(optimum async req size in bytes) - 4 */
226 #define PCI_AGP_STATUS_CAL_MASK 0x1c00 /* Calibration cycle timing */
227 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
228 #define PCI_AGP_STATUS_ITA_COH 0x0100 /* In-aperture accesses always coherent */
229 #define PCI_AGP_STATUS_GART64 0x0080 /* 64-bit GART entries supported */
230 #define PCI_AGP_STATUS_HTRANS 0x0040 /* If 0, core logic can xlate host CPU accesses thru aperture */
231 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing cycles supported */
232 #define PCI_AGP_STATUS_FW 0x0010 /* Fast write transfers supported */
233 #define PCI_AGP_STATUS_AGP3 0x0008 /* AGP3 mode supported */
234 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported (RFU in AGP3 mode) */
235 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported (8x in AGP3 mode) */
236 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported (4x in AGP3 mode) */
237 #define PCI_AGP_COMMAND 8 /* Control register */
238 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
239 #define PCI_AGP_COMMAND_ARQSZ_MASK 0xe000 /* log2(optimum async req size in bytes) - 4 */
240 #define PCI_AGP_COMMAND_CAL_MASK 0x1c00 /* Calibration cycle timing */
241 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
242 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
243 #define PCI_AGP_COMMAND_GART64 0x0080 /* 64-bit GART entries enabled */
244 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow generation of 64-bit addr cycles */
245 #define PCI_AGP_COMMAND_FW 0x0010 /* Enable FW transfers */
246 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate (RFU in AGP3 mode) */
247 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate (8x in AGP3 mode) */
248 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate (4x in AGP3 mode) */
249 #define PCI_AGP_SIZEOF 12
251 /* Slot Identification */
253 #define PCI_SID_ESR 2 /* Expansion Slot Register */
254 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
255 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
256 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
258 /* Message Signalled Interrupts registers */
260 #define PCI_MSI_FLAGS 2 /* Various flags */
261 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
262 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
263 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
264 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
265 #define PCI_MSI_RFU 3 /* Rest of capability flags */
266 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
267 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
268 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
269 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
272 #define PCI_PCIX_COMMAND 2 /* Command register offset */
273 #define PCI_PCIX_COMMAND_DPERE 0x0001 /* Data Parity Error Recover Enable */
274 #define PCI_PCIX_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */
275 #define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT 0x000c /* Maximum Memory Read Byte Count */
276 #define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS 0x0070
277 #define PCI_PCIX_COMMAND_RESERVED 0xf80
278 #define PCI_PCIX_STATUS 4 /* Status register offset */
279 #define PCI_PCIX_STATUS_FUNCTION 0x00000007
280 #define PCI_PCIX_STATUS_DEVICE 0x000000f8
281 #define PCI_PCIX_STATUS_BUS 0x0000ff00
282 #define PCI_PCIX_STATUS_64BIT 0x00010000
283 #define PCI_PCIX_STATUS_133MHZ 0x00020000
284 #define PCI_PCIX_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */
285 #define PCI_PCIX_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */
286 #define PCI_PCIX_STATUS_DEVICE_COMPLEXITY 0x00100000 /* 0 = simple device, 1 = bridge device */
287 #define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT 0x00600000 /* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */
288 #define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS 0x03800000
289 #define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE 0x1c000000
290 #define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS 0x20000000 /* Received Split Completion Error Message */
291 #define PCI_PCIX_STATUS_RESERVED 0xc0000000
292 #define PCI_PCIX_SIZEOF 4
295 #define PCI_PCIX_BRIDGE_SEC_STATUS 2 /* Secondary bus status register offset */
296 #define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT 0x0001
297 #define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ 0x0002
298 #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED 0x0004 /* Split Completion Discarded on secondary bus */
299 #define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC 0x0008 /* Unexpected Split Completion on secondary bus */
300 #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN 0x0010 /* Split Completion Overrun on secondary bus */
301 #define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED 0x0020
302 #define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ 0x01c0
303 #define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED 0xfe00
304 #define PCI_PCIX_BRIDGE_STATUS 4 /* Primary bus status register offset */
305 #define PCI_PCIX_BRIDGE_STATUS_FUNCTION 0x00000007
306 #define PCI_PCIX_BRIDGE_STATUS_DEVICE 0x000000f8
307 #define PCI_PCIX_BRIDGE_STATUS_BUS 0x0000ff00
308 #define PCI_PCIX_BRIDGE_STATUS_64BIT 0x00010000
309 #define PCI_PCIX_BRIDGE_STATUS_133MHZ 0x00020000
310 #define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */
311 #define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */
312 #define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN 0x00100000 /* Split Completion Overrun */
313 #define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED 0x00200000
314 #define PCI_PCIX_BRIDGE_STATUS_RESERVED 0xffc00000
315 #define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL 8 /* Upstream Split Transaction Register offset */
316 #define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL 12 /* Downstream Split Transaction Register offset */
317 #define PCI_PCIX_BRIDGE_STR_CAPACITY 0x0000ffff
318 #define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT 0xffff0000
319 #define PCI_PCIX_BRIDGE_SIZEOF 12
322 * The PCI interface treats multi-function devices as independent
323 * devices. The slot/function address of each device is encoded
324 * in a single byte as follows:
329 #define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
330 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
331 #define PCI_FUNC(devfn) ((devfn) & 0x07)
333 /* Device classes and subclasses */
335 #define PCI_CLASS_NOT_DEFINED 0x0000
336 #define PCI_CLASS_NOT_DEFINED_VGA 0x0001
338 #define PCI_BASE_CLASS_STORAGE 0x01
339 #define PCI_CLASS_STORAGE_SCSI 0x0100
340 #define PCI_CLASS_STORAGE_IDE 0x0101
341 #define PCI_CLASS_STORAGE_FLOPPY 0x0102
342 #define PCI_CLASS_STORAGE_IPI 0x0103
343 #define PCI_CLASS_STORAGE_RAID 0x0104
344 #define PCI_CLASS_STORAGE_OTHER 0x0180
346 #define PCI_BASE_CLASS_NETWORK 0x02
347 #define PCI_CLASS_NETWORK_ETHERNET 0x0200
348 #define PCI_CLASS_NETWORK_TOKEN_RING 0x0201
349 #define PCI_CLASS_NETWORK_FDDI 0x0202
350 #define PCI_CLASS_NETWORK_ATM 0x0203
351 #define PCI_CLASS_NETWORK_OTHER 0x0280
353 #define PCI_BASE_CLASS_DISPLAY 0x03
354 #define PCI_CLASS_DISPLAY_VGA 0x0300
355 #define PCI_CLASS_DISPLAY_XGA 0x0301
356 #define PCI_CLASS_DISPLAY_OTHER 0x0380
358 #define PCI_BASE_CLASS_MULTIMEDIA 0x04
359 #define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400
360 #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401
361 #define PCI_CLASS_MULTIMEDIA_OTHER 0x0480
363 #define PCI_BASE_CLASS_MEMORY 0x05
364 #define PCI_CLASS_MEMORY_RAM 0x0500
365 #define PCI_CLASS_MEMORY_FLASH 0x0501
366 #define PCI_CLASS_MEMORY_OTHER 0x0580
368 #define PCI_BASE_CLASS_BRIDGE 0x06
369 #define PCI_CLASS_BRIDGE_HOST 0x0600
370 #define PCI_CLASS_BRIDGE_ISA 0x0601
371 #define PCI_CLASS_BRIDGE_EISA 0x0602
372 #define PCI_CLASS_BRIDGE_MC 0x0603
373 #define PCI_CLASS_BRIDGE_PCI 0x0604
374 #define PCI_CLASS_BRIDGE_PCMCIA 0x0605
375 #define PCI_CLASS_BRIDGE_NUBUS 0x0606
376 #define PCI_CLASS_BRIDGE_CARDBUS 0x0607
377 #define PCI_CLASS_BRIDGE_OTHER 0x0680
379 #define PCI_BASE_CLASS_COMMUNICATION 0x07
380 #define PCI_CLASS_COMMUNICATION_SERIAL 0x0700
381 #define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
382 #define PCI_CLASS_COMMUNICATION_OTHER 0x0780
384 #define PCI_BASE_CLASS_SYSTEM 0x08
385 #define PCI_CLASS_SYSTEM_PIC 0x0800
386 #define PCI_CLASS_SYSTEM_DMA 0x0801
387 #define PCI_CLASS_SYSTEM_TIMER 0x0802
388 #define PCI_CLASS_SYSTEM_RTC 0x0803
389 #define PCI_CLASS_SYSTEM_OTHER 0x0880
391 #define PCI_BASE_CLASS_INPUT 0x09
392 #define PCI_CLASS_INPUT_KEYBOARD 0x0900
393 #define PCI_CLASS_INPUT_PEN 0x0901
394 #define PCI_CLASS_INPUT_MOUSE 0x0902
395 #define PCI_CLASS_INPUT_OTHER 0x0980
397 #define PCI_BASE_CLASS_DOCKING 0x0a
398 #define PCI_CLASS_DOCKING_GENERIC 0x0a00
399 #define PCI_CLASS_DOCKING_OTHER 0x0a01
401 #define PCI_BASE_CLASS_PROCESSOR 0x0b
402 #define PCI_CLASS_PROCESSOR_386 0x0b00
403 #define PCI_CLASS_PROCESSOR_486 0x0b01
404 #define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02
405 #define PCI_CLASS_PROCESSOR_ALPHA 0x0b10
406 #define PCI_CLASS_PROCESSOR_POWERPC 0x0b20
407 #define PCI_CLASS_PROCESSOR_CO 0x0b40
409 #define PCI_BASE_CLASS_SERIAL 0x0c
410 #define PCI_CLASS_SERIAL_FIREWIRE 0x0c00
411 #define PCI_CLASS_SERIAL_ACCESS 0x0c01
412 #define PCI_CLASS_SERIAL_SSA 0x0c02
413 #define PCI_CLASS_SERIAL_USB 0x0c03
414 #define PCI_CLASS_SERIAL_FIBER 0x0c04
416 #define PCI_CLASS_OTHERS 0xff
418 /* Several ID's we need in the library */
420 #define PCI_VENDOR_ID_INTEL 0x8086
421 #define PCI_VENDOR_ID_COMPAQ 0x0e11