2 ******************************************************************************
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3 * @file system_stm32f0xx.c
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4 * @author MCD Application Team
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5 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
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7 * 1. This file provides two functions and one global variable to be called from
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9 * - SystemInit(): This function is called at startup just after reset and
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10 * before branch to main program. This call is made inside
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11 * the "startup_stm32f0xx.s" file.
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13 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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14 * by the user application to setup the SysTick
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15 * timer or configure other parameters.
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17 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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18 * be called whenever the core clock is changed
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19 * during program execution.
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21 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
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22 * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
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23 * configure the system clock before to branch to main program.
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25 * 3. This file configures the system clock as follows:
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26 *=============================================================================
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27 * Supported STM32F0xx device
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28 *-----------------------------------------------------------------------------
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29 * System Clock source | HSI
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30 *-----------------------------------------------------------------------------
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31 * SYSCLK(Hz) | 8000000
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32 *-----------------------------------------------------------------------------
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33 * HCLK(Hz) | 8000000
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34 *-----------------------------------------------------------------------------
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36 *-----------------------------------------------------------------------------
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37 * APB1 Prescaler | 1
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38 *-----------------------------------------------------------------------------
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39 *=============================================================================
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40 ******************************************************************************
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43 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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45 * Redistribution and use in source and binary forms, with or without modification,
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46 * are permitted provided that the following conditions are met:
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47 * 1. Redistributions of source code must retain the above copyright notice,
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48 * this list of conditions and the following disclaimer.
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49 * 2. Redistributions in binary form must reproduce the above copyright notice,
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50 * this list of conditions and the following disclaimer in the documentation
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51 * and/or other materials provided with the distribution.
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52 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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53 * may be used to endorse or promote products derived from this software
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54 * without specific prior written permission.
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56 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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57 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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58 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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59 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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60 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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61 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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62 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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63 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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64 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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65 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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67 ******************************************************************************
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70 /** @addtogroup CMSIS
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74 /** @addtogroup stm32f0xx_system
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78 /** @addtogroup STM32F0xx_System_Private_Includes
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82 #include "stm32f0xx.h"
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88 /** @addtogroup STM32F0xx_System_Private_TypesDefinitions
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96 /** @addtogroup STM32F0xx_System_Private_Defines
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99 #if !defined (HSE_VALUE)
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100 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
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101 This value can be provided and adapted by the user application. */
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102 #endif /* HSE_VALUE */
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104 #if !defined (HSI_VALUE)
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105 #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
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106 This value can be provided and adapted by the user application. */
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107 #endif /* HSI_VALUE */
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109 #if !defined (HSI48_VALUE)
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110 #define HSI48_VALUE ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz.
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111 This value can be provided and adapted by the user application. */
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112 #endif /* HSI48_VALUE */
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117 /** @addtogroup STM32F0xx_System_Private_Macros
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125 /** @addtogroup STM32F0xx_System_Private_Variables
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128 /* This variable is updated in three ways:
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129 1) by calling CMSIS function SystemCoreClockUpdate()
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130 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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131 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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132 Note: If you use this function to configure the system clock there is no need to
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133 call the 2 first functions listed above, since SystemCoreClock variable is
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134 updated automatically.
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136 uint32_t SystemCoreClock = 8000000;
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138 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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139 const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
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145 /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
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153 /** @addtogroup STM32F0xx_System_Private_Functions
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158 * @brief Setup the microcontroller system.
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159 * Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
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163 void SystemInit(void)
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165 /* Reset the RCC clock configuration to the default reset state ------------*/
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166 /* Set HSION bit */
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167 RCC->CR |= (uint32_t)0x00000001U;
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169 #if defined (STM32F051x8) || defined (STM32F058x8)
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170 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
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171 RCC->CFGR &= (uint32_t)0xF8FFB80CU;
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173 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
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174 RCC->CFGR &= (uint32_t)0x08FFB80CU;
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175 #endif /* STM32F051x8 or STM32F058x8 */
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177 /* Reset HSEON, CSSON and PLLON bits */
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178 RCC->CR &= (uint32_t)0xFEF6FFFFU;
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180 /* Reset HSEBYP bit */
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181 RCC->CR &= (uint32_t)0xFFFBFFFFU;
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183 /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
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184 RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
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186 /* Reset PREDIV[3:0] bits */
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187 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
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189 #if defined (STM32F072xB) || defined (STM32F078xx)
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190 /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
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191 RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
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192 #elif defined (STM32F071xB)
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193 /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
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194 RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
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195 #elif defined (STM32F091xC) || defined (STM32F098xx)
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196 /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
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197 RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
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198 #elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
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199 /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
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200 RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
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201 #elif defined (STM32F051x8) || defined (STM32F058xx)
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202 /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
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203 RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
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204 #elif defined (STM32F042x6) || defined (STM32F048xx)
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205 /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
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206 RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
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207 #elif defined (STM32F070x6) || defined (STM32F070xB)
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208 /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
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209 RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
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210 /* Set default USB clock to PLLCLK, since there is no HSI48 */
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211 RCC->CFGR3 |= (uint32_t)0x00000080U;
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213 #warning "No target selected"
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216 /* Reset HSI14 bit */
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217 RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
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219 /* Disable all interrupts */
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220 RCC->CIR = 0x00000000U;
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225 * @brief Update SystemCoreClock variable according to Clock Register Values.
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226 * The SystemCoreClock variable contains the core clock (HCLK), it can
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227 * be used by the user application to setup the SysTick timer or configure
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228 * other parameters.
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230 * @note Each time the core clock (HCLK) changes, this function must be called
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231 * to update SystemCoreClock variable value. Otherwise, any configuration
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232 * based on this variable will be incorrect.
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234 * @note - The system frequency computed by this function is not the real
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235 * frequency in the chip. It is calculated based on the predefined
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236 * constant and the selected clock source:
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238 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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240 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
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242 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
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243 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
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245 * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
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246 * 8 MHz) but the real value may vary depending on the variations
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247 * in voltage and temperature.
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249 * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
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250 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
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251 * frequency of the crystal used. Otherwise, this function may
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252 * have wrong result.
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254 * - The result of this function could be not correct when using fractional
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255 * value for HSE crystal.
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260 void SystemCoreClockUpdate (void)
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262 uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
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264 /* Get SYSCLK source -------------------------------------------------------*/
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265 tmp = RCC->CFGR & RCC_CFGR_SWS;
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269 case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
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270 SystemCoreClock = HSI_VALUE;
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272 case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
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273 SystemCoreClock = HSE_VALUE;
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275 case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
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276 /* Get PLL clock source and multiplication factor ----------------------*/
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277 pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
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278 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
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279 pllmull = ( pllmull >> 18) + 2;
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280 predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
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282 if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
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284 /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
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285 SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
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287 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
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288 else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
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290 /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
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291 SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
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293 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
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296 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
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297 || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
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298 || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
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299 /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
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300 SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
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302 /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
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303 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
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304 #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
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305 STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
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306 STM32F091xC || STM32F098xx || STM32F030xC */
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309 default: /* HSI used as system clock */
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310 SystemCoreClock = HSI_VALUE;
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313 /* Compute HCLK clock frequency ----------------*/
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314 /* Get HCLK prescaler */
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315 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
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316 /* HCLK clock frequency */
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317 SystemCoreClock >>= tmp;
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332 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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